The Research On Integrating Process Of High Density System

System-in-package(SIP) is an emerging technology developed in recent years to satisfy the demand of module system hardware. Compared to SOC, SIP has the advantages of high flexibility, repairability and reliability. Therefore, SIP technology is becoming an interesting subject. The key techniques for SIP include system design technique,substrate interconnection,passive component integration, chip interconnection, 3D stacked-layer assembly and system detection, etc. The system integrating process is the core technology for implementation of SIP. So, it is of great significance to study packaging technologies for high density SIP.Based on stacked-layer 3D packaging technology, process technology is developed, including embedding of passive components, wafer thinning, stacked chips assembling, low-arc golden-wire bonding, bumping on chip and stacked layer interconnecting and assembling. By using mature MCM-D(thin-film integration) process technology thin-film SIP samples are fabricated. Also major process flow and key process step control techniques were explored.The research subjects and achievements in this paper are listed as follows:1. An in-depth analysis and research of implementation methods and technical approches for high density system integration process were made. It is pointed out that fabrication techniques for substrate with embedded multilayer wiring, chip-stacking and assembling technique and fabricating of wafers with fine-pitch bumping should be investigated for the development of system-in-package.2. Fabrication techniques for substrate with embedded multilayer wiring is investigated; process flow for multilayer wired substrate is explored; characteristics of interlayer BCB material process are analyzed in particular; fabrication technology for BCB dielectric via is developed; and finally, Si-based substrates with 3-active-layer wiring are fabricated.3. Wafer stacking and assembling technology is investigated; wafer stacking process is developed and problems in interconnect process for low-arc wire bonding of stacked wafers are solved.4. Process technology for fine-pitch bumping is investigated; an in-depth analysis is made on layout design, fabrication process and key techniques of bumping. Bottlenecks of process are solved including thick photoresist photolithography for bumping preparing, UBM layer formation and solder bumping reflow. fine-pitch bumpings with fine pitch of 290μm and diameter of 190μm are prepared. Finally, SIP samples were fabricated by integrating each process technology and optimizing process flows.5. The electric parameters of our SIP sample as below: Transceiver frequency: 2.7GHz-3.5GHz; emitting power: ≥-20dBm; Gain of receive channel: ≥20dB; IF: 30MHz-60 MHz. The SIP sample based on thin film active silicon substrate meets the design requirements. This reaearch is nessary for the urgent need on integration, digitization and miniaturization of RF transceiver and A/D process system.