Research On FPGA Simulation For VLSI Test Compression Technology

With the rising complexity of integrated circuits and the continuous progress of semiconductor process technology, the increasing difficulty of test and the mass of test data have become obstacles to the development of integrated circuits test. To solve the problems, many scholars put forward many excellent DFT. BIST is such an effective, high-speed and reliable DFT. Typically, LFSR is a simple structure to generate test vectors. However, because the test vector generated by LFSR is pseudo-random, these parts of vectors usually do not achieve the fault coverage of the test requirements, so LFSR cannot measure unpredictable failures. Generally, we use approach based ATPG generate deterministic fault, which is an effective supplement to improve fault coverage. However, in the VLSI test, deterministic test data is significantly massive. To reduce the size of ROM in the chip, numerous data must be compressed.Since there are a large amount of high power problems caused by massive test data during the test, in this thesis, we present vectors reseeding test compression scheme. First, based on low power mode generated, we divide a test vector into some coding blocks, and then connect the coded test vectors and encoded them as the seed vectors. Experimental results show that this compression scheme can reduce the number of reseeding. This approach greatly reduces storage space of the seeds, and effectively reduces test power. It also improves the reliability of the circuit. As a result, the scheme is better fit for the BIST design.Since FPGA is a flexible, efficient, high reliability, widely applied programmable chips, we use FPGA design and simulate implementation circuit. In this thesis, based on DFT design concept, we combined with FPGA hardware design platform, and firstly designed and simulated ROM, ROM for Controller, LFSR, some counters, scan chain and generated control of nuclear for test vectors. Then, we integrated this various modules into a complete implementation circuit. After the synthesis and simulation work, we can load bit stream to the Spartan-3E family FPGA development board for verification. The simulation process and results proves this compression scheme has practical feasibility. Finally, in the implementation circuit simulation, we analyze resource utilization and power generation in the test. It shows that hardware circuit for simulation costs smaller area and produces lower power consumption. The proposed scheme can be effectively applied to the design of FPGA-based BIST. Thus, it can achieve the purpose of reducing the test difficulty, the chip area overhead, test time and improving fault coverage.