Research On Optimization Techniques For SoC Test Scheduling

With the rapid development of electronic technology integration, So C(System-on-a-Chip) is more widely used, it use the technology of IP cores reuse and has high integration, more small size, more stable performance, short development cycle and many other advantages. However, the chip integrates more and more functions, so that the structure is more complex, the number of internal IP core continues to grow, there is a sharp increase in test time. To solve these problems, the author designed a parallel test task scheduling algorithm based on ant colony algorithm, combined with the algorithm designed a test architecture. With QT development framework and FPGA chip,the author built software and hardware platforms of experimental verification of So C test. Finally, experimental verification test time optimize performance of scheduling algorithm The main contents of this paper are:Firstly, the overall research plan of this topic was proposed.The author have a research on the relevant technology of So C test, design for testability, BIST, boundary scan test, scan testing techniques in-depth, design a parallel scan test method, which has advantages of a high resource utilization and short test time.Study the test architecture, both from the test wrapper and test access mechanism to expand design. The author design test wrapper based on IEEE1500 standard and test bus access mechanism(TAM). The author divided test scheduling problem and design IP core parallel test scheduling algorithm in order to reduce test time.Secondly, test architecture was designed. The author descripted function of boundary register, bypass register, instruction register with verilog language and packaged them into modules, they interconnected with each other to form a complete test ring; the author designed a test Bus bit divided test access mechanism. Simulated functional correctness of structure with Modelsim software and verified the function of design.Then, on the basis of comparative analysis test scheduling classical algorithms, the author propose parallel scheduling algorithm for IP core test based on ant colony optimization algorithm. Based on examples, the scheduling method in this paper was compared with linear programming and genetic algorithm, experimental results show that this algorithm can get the shortest total test time task scheduling sequence.Finally, the author set up an experimental platform for So C testing. d695 of ITC’02 standard test circuits was designed for testability and used as the circuit under test. The author designed experiments under different TAM bus width, Compared actual test time of the scheduling method in this paper and other methods, it verify optimize performance of the method in test time.