Study Of Signal Processor Architecture Based On FPGA Vector Coprocessor

High–speed and real-time processing are two obvious requirements for radar signal processing. Generally, the signal processing includes a great massive of operations of similar type of data. So, in this paper, vector processing technology and coprocessor were proposed to implement the data operations..Firstly, the basic algorithms for radar signal processing were introduced. And based on the analysis of the existing radar signal processing technologies, the radar signal processing technology based on vector processing technology and coprocessor were proposed, which mainly includes instruction fetch and decode unit, vector registers unit, vector operating unit, loading or storing unit, instructions or data cache unit, memory management unit, bus interface unit and so on.Secondly, in considerations of the advantages of both the FPGA and vector processing, on the basis of Alti Vec, this paper designed a vector co-processor by using FPGA to complete the vector processing of unit operates on both integer and single floating-point and other relevant units. This paper aimed at exception operational issues that can’t be ignored in floating-point operation process, with IEEE 754 floating-point standard, a custom floating-point data format with two flags was proposed, and completed the design and simulation of floating-point arithmetic modules. It has been completed that vector add, vector subtract, vector multiply, vector multiply add, vector sum and vector dot product with use of these basic operating units.Finally, applying the thinking of vector processing, matrix-matrix multiply, FIR Filter and FFT algorithm have been analysized and simulated with FPGA using vector instructions, and the simulation results have been contrasted with the output results of Matlab and proved to be correct.At last,LFM pulse compression simulation has been accomplished with the above-mentioned method of vector processing.