| HUD is an airborne integrated electronic display device. Important flight parameters in the form of graphics and characters are projected to electric / optical display device in front of cockpit. Higher requirements of resolution, display quality and real time are put forward for HUD in the next generation fighter. In response to these needs, further research is carried out in this paper with "HUD graphics display system" support. The development of new graphics generating and video processing core system is completed. The system receive graphics and video control signal sent by upper CPU. Graphics generation and its anti aliasing with high quality is realized, while real-time video is processed. The algorithm research and realization based on FPGA of graphics generating, video processing, and DDR3 memory management are completed in this paper. The main work is as follows:(1) System logic diagram is designed and optimized. Parallel processing of graphics and video is realized, and the throughput of DDR3 is reduced, so the overall performance is improved. According to the system functional requirements, logic of DDR3 interface is designed and optimized. DDR3 throuphout of system logic diagram is optimized from 1728.4 MB/s to 1186.5MB/s, which is reduced by 31.4%. So, the optimized system effectively reduces the load on DDR3 and improves overall performance.(2) An improved line anti-aliasing algorithm, fast algorithm for generating arc, triangle filling and edge anti-aliasing algorithm are proposed in this paper. The improved line anti-aliasing algorithm effectively reduces Hemp flowers phenomenon of small angle line, so it is applicable to any angle line and arc. The improved fast algorithm for generating arc overcomes the angle discrimination, reduces the use of logic resource, and improves the speed of circle drawing. The improved triangle filling and edge anti aliasing algorithm has small quantity, and effectively improves the display effect of the filled triangle. At the same time, two-dimensional graphics fast generation and its anti aliasing are implemented based on FPGA, including point, horizontal line, slash, circle, arc, triangle filling, rectangle filling, circle filling, character, etc..(3) An improved video rotation mapping method is put forward and "Catch-up" frame replication algorithm is realized. The improved video rotation mapping method can make video rotation processing with only two lines cache, which effectively reduces the delay of video rotation, occupies less memory space, and is suitable for hardware implementation. "Catch-up" frame replication algorithm ensures that the current output of the frame is the latest write full frame. The maximum delay is reduced from 104 ms to 36.8ms, which makes speed improve 1.8 times. It improves the real-time performance of the system effectively. At the same time, video processing module is designed and implemented based on FPGA, including design and debugging of logic module such as video signal acquisition of PAL format and DVI format, scaling and rotation, contrast and brightness adjustment, DVI format output.(4) DDR3 multi port read-write storage management is designed and implemented. Two pieces of DDR3 are used respectively to realize high speed read and write, which simplify the complexity of multi port’s read and write, and improve the parallel processing speed. Each data request is set to be an interrupt, so as to solve the conflict of data storage.Performance test and result analysis are completed. The test results show that anti-aliasing processing algorithm proposed effectively improves the serrated phenomenon of small angle, so as to make the image becomes smoother; video after superimposed has color uniformity, and video processing delay is controlled within 40 ms, which meets the requirement of real time. |
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