Research On Power Gating Technology Of High-performance Microprocessor

As the high-performance microprocessor design went into the era of multi-core and multi-threaded processor, the method of integrated circuit production is different from the old times. The traditional Moore’s low is facing unprecedented challenges, and the power consumption problem becomes one of the primary problems that constrains to the development of the processor design. Especially when the IC technology gets into the 90 nm size, the leakage power issues become more prominent. The traditional low-power technology cannot effectively control the leakage power, so the new low-power technology came into being.Based on the study of the codes in the microprocessor X, we analyzed its structure and function.On this basis, we add a power gating design into the Microprocessor.When the workload is not heavy, we turn off some of the processors. When a larger workload comes, we wake up the sleeping processor cores and put them back into the working state by restoring their power. And we design a power management control unit(PMC) to complete the task of controlling the process of power up and down.Additionally, we put forward a method that can control the power of the SRAM automatically. By increasing the power gating design to the microprocessor X, we reduce the power consumption of the processor.Firstly, we divide the processor into nine power domains, design the power modes,and complete the overall low-power design for microprocessor X. Then by writing standard low-power design format file(CPF) we put the design intention on the processor. We put forward a sequence for the signal control when power up and down.Finally we prove that our design is successful from simulation and verification.Based on the characteristics of the processor, to realize the automatic control of the power up and down sequence, we design the power management control unit(PMC). In detail, we propose a design for the PMC, and analysis the structure of the PMC,intruduce the working principles and the state transitions of PMC. Then we write verilog code to implement the design. Finally through the preparation of test stimulus,we put the CPF file together with the codes of microprocessor X into simulation tests.By observing the waveform, we prove that the PMC works well.In this paper, we study layout related technologies and propose a method for power network design. Making comparison between different kinds of structures on power gating switches and using RedHawk software to test the performance on rush current and IR drop. And we take test for power switches on the interval time between differentchains of the daisy chain switches. Finally we propose a parallel fine structure of power switch which contains four chains.Additionally, we try to control the power of microprocessor X in a fine-grained way by add power gating technic to SRAM. We proposed an instruction-buffer-based loop detecting mechanism. Once loop detected, the instruction cache can be bypassed and power gated. Simulation results show that it can reduce dynamic and static power efficiently, and also bring a positive performance improvement.