Structure Design Optimization And Overhead Evaluation For Parameterized Cluster Based Hierarchical Network-on-Chip

Network-on-chip(NoC) is a promising solution for on-chip multi-core interconnection. NoC can improve the flexibility and network bandwidth of traditional CMP system. However, with the increasing number of cores integrated on chip, the flat NoC structure is facing communication bottle- neck of large latency and low throughput. With upper transfer layers, hierarchical interconnected NoC was proposed which may provide larger communication channel bandwidth and more transfer paths and is the effective interconnection scheme for large scale high-performance multi-core systems.There existing problems for hierarchical NoC topology are as follows.(1) Present hierarchical topologies are not flexible enough for different size of network, and the inter-layer traffic is not balanced.(2) For the delay aware design, it is hard to explore hierarchical design space to obtain optimized structure.(3) For the multi- layers of hierarchical network, it is not easy to evaluate area overhead accurately. Concerning the above problems, this paper did contributions to the new design method for hierarchical NoC structure as well as its optimization. Additionally, we evaluated the resource overhead of hierarchical NoC structures. The main contributions are as follows:1. For the non-flexible design and unbalanced inter-layer traffic problem of the existing hierarchical interconnect structures, we proposed the parameterized clustered hierarchical NoC(PHNoC) design method. 2X2 and 4X4 Mesh clusters are used as the unit of inter- layer structure, and three parameters are introduced for setting up the cluster size and number of cross-layer links, so as to achieve the design flexibility under different scale of network. We also designed cross- layer flow controlling dead lock free routing algorithm, which uses cross-layer flow-control parameter to control inter- layer flow. The PHNoC method could make the hierarchical designed structure shorter latency and higher throughput. Under nonuniform traffic patterns, compared to 2DMesh PHNoC structures lowered latency by 18.76%, and improved throughput by18.57%.2. Existing hierarchical NoC are designed with experience, in order to effectively explore the hierarchical NoC design space for low- latency targets, we proposed a latency aware hierarchical mesh NoC structure optimization algorithm(LAHNS). Firstly, we established the hierarchical mesh parameters model(HMPM), which was based on PHNoC method. Then, based on HMPM and traffic communication probability distribution we built end-to-end latency analytical model for hierarchical NoC. And finally using simulated annealing algorithm, we can get the latency optimized structural parameters. Experimental results showed that the latency model accurately predicted NoC delay of up to 98%, and the LAHNS algo rithm could generate structures with much reduced the latency, and the larger the system the more obvious effects.3. For the inaccurate and complicate of traditional evaluation for area overhead of hierarchical NoC, we proposed a Node-degree classified based area overhead evaluation model(NDCB) for hierarchical Mesh NoC. As the router node-degree associated with its location, based on HMPM model we established router and link quantity model, and with Orion area model we got accurate network area and link cost model. Both the experiment and ISE synthesis results demonstrate that NDCB model was accurate, and the results from traditional method without node-degree classified had big deviation; Using NDCB we also found that two-tier hierarchical Mesh resources increased by 10% in the 256 node, while three increased by 20%, thus the trade-offs of resource performance need to be considered.