The Design And Application Of SPI Interface In Neural Network Accelerator Chips

With the development of technology, the application of artificial neural networks has occured significant changes in past few years and now the technology is widely used in computer vision, speech recognition, natural language processing, audio recognition and so on. But traditional conventional instruction sets, such as x86, ARM and etc require hundreds or even thousands of instructions to complete a neuron process, which is inefficient. Machine learning accelerator chip is directly facing the large-scale processing of neurons and synapses, it uses an instruction to complete a deal with a group of neurons, which greatly improves the efficiency of machine learning, so it has significant meaning to research this type of processor.Based on the functional requirements of neural network accelerator chip, because of the complexity of high-speed interface protocol, it is hard to accurately test the chip and takes long-debug cycle. The SPI interface which it’s protocol is simple, easy to integrate and moderate speed enables accurating simulation fast and has good guidance for subsequent design and debugging.In the design of SPI module, we use the method of bottom to up approach, and divide the SPI module into several sub-modules, then design five major sub-modules. We adapt module integration of IP technology, and integrate the sub-modules to achieve a fully functional SPI modules. The SPI module support the function which include master/slave select, four clock transmission mode, high/low data first transmission, clock frequency divide, multi-slave communication, interrupt and so on. As a result of AXI interface standards, it is easily to transplant and fit IP reuse standards, and it can be used as a generic SPI core into other applications.After completing the SPI module design, we use three different kinds of scheme to test the module, followed by functional simulation, FPGA test, chip testing of finished products. In functional simulation, we first verify the sub-module and then verify the whole module. In the FPGA and chip testing and validation process, we use hardware and software co-verification thoughts. And in accordance with the test requirements, we use virtual serial port technology to design usb adapter to spi protocol circuit, the circuit not only simplifies the preparation of spi driven in Ubuntu operation system, but also it can not affect the data transmit speed between spi driver based on Ubuntu operation system and neural network accelerator.After finishing functional, FPGA and chip verification, we get a conclusion that SP1 interface module is designed properly and the function fits design requirements. We transmit data through SPI port to neural network accelerator chip and make comparison between x86 CPU and our chip in the same environment, the test results show that the neural network accelerator performance far superior than general purpose processor, and it has a good prospect.