FPGA-based Accelerator For Convolutional Neural Network

Convolutional Neutral Network is a multi-layer perceptron, derived from Artificial Neutral Network. It is a sensitive sensor for pattern fearture extraction, which is widely used in recent years because of its high adaptability to image translation, scaling, tilt and other forms of distortion. Currently, the convolution neural network is mainly implemented on general-purpose processors. However, software-based method can not fully exploit the parallelism of the convolution neural network. The real-time performance and power consumption can not meet the needs of applications. Since FPGA is resource-rich, flexiable and can be equipped with short development cycle, more and more researchers begin to develop application on FPGA based on convolutional neural network.In this thesis, we analyze the parallel features of convolution computation from the perspective of computation efficiency and data reuse, and study the activation function implementation, based on the model of convolution neural network. And on this basis, we design a FPGA-based convolutional neutral network accelerator. The accelerator is based on HOST+FPGA framework, and is pipelined for operation efficiency; it fully uses convolution computation parallelism to balance the computation efficiency and bandwidth requirement; and its activation function is realized by PWL approximation, which balances the flexibility and resource consumption. In the handwritten numeral recognition experiment, the accelerator can perform 36 multiply-accumulates per cycle, and can achieve a peak performance of 0.915 GMACS/s, which is 5.65x faster than the general CPU, while the power comsuming is only 3.07 percent of the general CPU.