Design Of High Speed Serial Transmitter Whose Data Rate Is 5Gb/s Based On RapidIO Protocol

In modern society, the interaction of information becomes more and more frequent. The increasing interaction of mass data makes the high speed transmission become more demanding. High speed serial interface with the higher data rate has been widely researched and applied, and it has recently replaced parallel interface. The thesis studies the high speed serial interface transmitter as follows:Based on the system structure, the thesis analyzes the structural features of CML(Current Mode Logic) transmitter. In order to fulfill the demand of Signal Integrity, the thesis also designs a big-swing CML transmitter with data rate at 5Gb/s. According to the high accuracy requirements of tail current precision for CML transmitter, the thesis designs a bandgap with adjustable output current.Based on the theoretical analysis, the thesis analyzes the equivalent circuit of the output driver and finds the relationship amongst output amplitude, de-emphasis and tail current. This leads to the finding of universal formula of the output signal swing.Based on the electrical design, the thesis uses composite structure serializer to serialize 10-bit parallel input data. It also uses the bias current filtering technique and inversely proportional reduction technique to reduce the power consumption and improve the noise immunity of common mode. To ensure the output current meet the demand of output driver, the output current of the bandgap can be controlled by switch, the thesis also uses low voltage power supply to design output driver of CML transmitter, reducing the overall power consumption of the CML transmitter.In the end, the thesis designs the layout of CML transmitter and bandgap by using Huali 40nm CMOS Process. The area of CML transmitter is 153*237um2 and the area of bandgap is 159.14*66um2. The layout of output driver with low voltage power supply is designed by using Smic 55nm CMOS Process. The area of the output driver is 164*115 μ m2. The simulation results show the following:the output voltage of bandgap is 488mV-499mV, the output current is 89uA-121uA, the drift is 20ppm. The jitter of CML transmitter is 2.70ps(RMS) at 5Gb/s. The jitter of output driver with low voltage power supply is 2.696ps(RMS). The test results show:The output voltage of bandgap is 510+1 OmV, the output current is 100 ± 1 OuA by adjusting.