Design Of High Efficiency Envelope Amplifier In CMOS Technology

Wireless communication technique has entered era of 4G, and researches on 5G communication are in full swing. Modern wireless communication systems pursuit high data rate service with limited spectral resources. Such signals have high value of peak-to-average power ratio caused by non-constant envelope modulation schemes.High peak-to-average power ratio signals cause the power amplifiers(PAs) to operate at a large back-off region of poor efficiency. It urges people to solve this problem.Envelope tracking is a dynamic power modulation technique. It can significantly boost the PAs efficiency in its back-off region. Envelope amplifier, which provide the dynamically modulated power supply to PA, is a key block in envelope tracking system.The efficiency of envelope amplifier directly determines the efficiency of the whole envelope tracking system. Meanwhile, with the increasingly matured CMOS analog circuit technique, it has become an indispensable manufacturing process in commercial communication integrated circuit industry. Research on CMOS integrated envelope amplifier is important for envelope tracking technique applied to micro base stations and low power mobile devices in the near future. This paper systematically studies CMOS integrated envelope amplifier. And it focus on the efficiency improving method for envelope amplifier. The major work of this paper is as follows:1. Envelope tracking technique is introduced. Its structures and efficiency improving principle are analyzed. Several envelope amplifier architectures are sketched.And their principles and relative merits are analyzed.2. Hybrid envelope amplifier architecture is introduced. Its circuit principle and efficiency are analyzed. Some necessary formula derivation and ideal functional simulation are performed.3. An envelope amplifier IC for 5MHz WCDMA application based on Globalfoundries 0.18 um CMOS technology is designed. It employs hybrid envelope amplifier architecture. Under 3.3V power supply, the measurement results show that it achieves output power of 27.5d Bm and efficiency of 74%. Power dissipation and chip area of the envelope amplifier IC are 24 m W and 0.5mm2, respectively. All the measured performances of the designed chip meat the design requirements.4. An improved hybrid envelope amplifier architecture is analyzed, in which an additional switching converter is added. And its circuit principle is discussed. This architecture has an efficiency improvement compared to the traditional one. Then an envelope amplifier IC for 10 MHz LTE application based on TSMC 0.18 um CMOS technology is designed. It employs the proposed improved dual-switch hybrid envelope amplifier architecture. Under 3.3V power supply, the simulation results show that it achieves output power of 28 d Bm and efficiency of 84.6%, which exhibits a 8%efficiency improvement. Power dissipation and chip area of the proposed envelope amplifier IC are 35.2m W and 0.9mm2, respectively. All the measured performances of the proposed chip meat the design requirements.