Design Of 64 Bit High Performance Adder Circuit Based On Kogge-Stone Algorithm And Domino Logic

High performance computing technology is very important in protecting the national security, promoting the progress of science and technology and promoting the development of economy. Adder circuit is the most basic circuit of the CPU circuit, so the adder circuit design is very important.For the selection of structure and logic, by comparing many high-speed adders such as Carry Look Ahead Adder, Kogge-Stone Adder, Brent-Kung Adder, and finally determined to use the 4-ary Kogge-Stone tree to design 64-bit adder. By comparing CMOS logic, DCVSL logic and dynamic logic, finally chose dynamic logic.The design used hierarchical design method. The carry generation and the carry propa-gation circuit, the operating circuit and carry generation circuit used dynamic structure. The summation circuit used static structure. In this paper, it described and designed every circuit unit and constructed the binary tree structure, then completed the whole circuit.A variety of optimization methods were used in this paper. It added the charge retention device in order to solve the problem of charge leakage and optimized the size of charge re-tention device. Except for the first stage dynamic circuit, it removed the evaluation transistor in dynamic logic to reduce the area and improve the speed. The paper designed the circuit structure of the clock, and the clock can meet the requirement of dynamic Domino logic. According to the estimate method of the optimal power supply voltage, the working voltage of this design used 1.2V supply voltage. In the design of each module circuit, the higher performance was obtained by adjusting the size of the transistor.This design used IBM 0.18um technology, and it used Cadence to get circuit simulation. The result shows that when the clock frequency is lGHz, the adder’s worst-case delay is 1.01ns, the power consumption is 19.4mW.