Energy Efficiency Optimization Of The Equalized Architecture For High Speed Links And Design Of A Fractionally-spaced Feed-forward Equalizer

With the rapid developments of Cloud Computing, Big Data and Internet of Things, people have ever growing requirements on the bandwidths of communication systems. Meanwhile, they also want to keep the power consumption within a reasonable range. So, it is getting more and more attention that how to transport high-speed data in a low-cost but reliable way. This thesis firstly presents a working flow which can search out the most energy-efficient equalizer architecture given the data rates, channel and link specifications. The flow combines link statistical analysis technique and transistor-level circuit power modeling technique, providing both feasibility and accuracy. Various equalization architectures that satisfying link constraints can be got using statistical technique. Furthermore, the energy efficiencies of various equalizers can be estimated by power modeling technique. Jointly, the total energy efficiency of each equalized combination can be compared, thus filtering out the most energy efficient equalization architecture.This dissertation also proposes a 6.25Gb/s+4-taps,1/3 symbol rate spaced feed-forward equalizer (FFE). The active delay line is implemented with source capacitive degeneration circuits to achieve high bandwidth, plus capacitance and resistor calibration to ease the harmful effects of processor corner variation. In addition, the output buffer utilizes two on-chip inductances for amplitude and bandwidth. Fabricated in 180-nm CMOS technology, the chip occupies 0.49mm2, now in production. Post simulations have shown that proposed FFE can work properly and effectively with 6.25Gb/s and lOGb/s severely distorted signal, reduce most of the inter-symbol interference and restore the eye opening.With nowadays rapidly developed communication systems, the proposed energy efficiency optimization flow of equalized architecture helps to relieve high-speed links from rate versus power dilemma, also the presented FFE is valuable to high-speed receiver design.