Design Of High Reliability Flash Memory Based On P-Channel Memory Cell

Flash memory is widely used in SoC. The applications of high density data storage and embedded systems are continuously increasing. Along with the progress of the technology, transistor feature sizes down to ten nanometer order of magnitude. Small process deviation will make challenges to Flash memory design.In this paper, I focus on the reliability of the Flash memory. I do some optimization for the peripheral circuits of the Flash memory. The 8Mbits nonvolatile memory is based on 0.18μm standard CMOS process. The system is built on Cadence Virtuoso, Hspice is used to perform module functional simulation, Hsim software is used to do whole circuit simulation, circuit layout is drawn using Laker.The main content and the research object of this paper is:Firstly, this article analyzes which channel of floating gate MOS used to the memory cell. And then compares the p-channel with n-channel floating gate MOS’s reliability performance. The reliability performance of p-channel is better than n-channel. So this paper chooses the p-channel floating gate MOS as a memory cell.Secondly, this paper studies peripheral circuit of the Flash memory. I analyze the traditional circuits of the peripheral circuits, and find out the disadvantages of each, then redesigne the circuits to meet the requirements with the help of hspice.In addition, in the last chapter of this paper, I first briefly introduce the layout design and wiring rules. And then I briefly introduce the IP of this project. After that, I do the overall simulation and especially analyze read, write, and erase operation.