High-performance Implementation Of Image Enhancement Based On FPGA

Currently, image processing has been applied to all aspects of people’s lives, such as medical, transportation, aerospace, industrial control etc.. Its importance stems from two main application areas: improving the image information for people to explain easily; Process the image for storage, transmission and representation, so that the image could be understood by machines automatically.Image enhancement is generally applied to image pre-processing stage. We needn’t consider what caused the degradation of the image. What we consider is how to highlight the section that we interested, suppress the section that doesn’t matter. The image which we received will be processed in order that can be analyzed easily in the next stage.In this stage, the notable feature is that the algorithmsare relatively simple, but there is a large number of data that we need to deal with duly. The challenge that we are facing is to deal with the huge amount of data in time, especially in areas such as transportation, military, aerospace and so on.FPGA is a programmable hardware, providing an effective solution for the real-tie image processing. This chip has the speed of ASIC and the flexibility of DSP. The main work of this paper is to study how to realize the high speed image processing in FPGA. The work of this paper is focused on the design of circuit structure, rather than the research of algorithm.Firstly, this paper introduced the structure of FPGA, and the method of designing hardware circuit. Then, by analyzing the characteristics of the algorithm, this paper designed three modules, include median filter, histogram equalization and two-dimensional fast Fourier transform, which can be used in the frequency domain of real-time image processing. Particularly, about the median filter, this paper makes full use of the binary characteristics of hardware, and generates the median data by bit. This circuit structure can save the resource consumption and increase the processing speed. In the histogram equalization circuit, an external memory, DDR3 SDRAM, is used in order to cache the image data. And ping-pang structure is also used, so that this circuit could process image of large size quickly.In this paper, the consumption of resources and the speed that can be achieved of the corresponding circuit module was given in detail. The circuit modules designed in this paper can be transplanted to other systems easily.