Study On Architecture Of ECC Codes And Evaluation Methodfor NAND Flash Memory

NAND flash memory has been widely applied in electronic storage systems. With technology scaling and storage density increasing, the bit error rate in NAND flash memory become more and more serious. As bit error rate in high-density NAND flash memory grows fast, common BCH codes cannot meet the error requirement of NAND flash memory. It is a trend to decreasing the code-rate of BCH codes for better performance, leading to effective capacity of NAND flash memory decreasing. In the future, the design of error correction code(ECC) for NAND flash memory needs to make a trade-off between reliability and storage capacity. How to evaluate ECC in NAND flash memory has become a problem. Due to superior performance and close to Shannon limit, low-density parity-check codes(LDPC)has been proposed to be ECC in next generation NAND flash memory. Decoding of LDPC codes needs soft information to obtain good performance, but extracting soft information from NAND flash memory is very difficult and costly. In consideration of the above problems, the work in this paper mainly focuses on the following aspects.This paper studied a new method to evaluate the overall performance of ECC for high-density NAND flash memory. The concept of error-free information capacity(EIC) was proposed to evaluate the performance of ECC for NAND flash memory. The new method simultaneously considers the capacity and reliability of NAND flash memory. Under different channel models of NAND flash memory, EIC was calculated and analyzed based on different ECCs. It was found that ECCs with medium code rate can improve the integrated performance of NAND flash memory.An ECC structure for NAND flash memory was presented, it was based on concatenation of block BCH codes and LDPC codes. In the proposed ECC structure, blockBCH codes were used to generate coarse soft information based on hard flash reads for LDPC codes. The proposed ECC structure could compatible with common BCH codes used in NAND flash memory. To meet the requirement of NAND flash, a rate-0.92 ECC based on the proposed structure was designed. Simulation showed that, although the blockBCH codes generatedcoarse soft information for LDPC codes, compared to common rate-0.92 BCH codes, the purposed ECC achieved double performance. The purposed ECC structure is evaluated by EIC in the end. Compared to rate-0.85 BCH code, the purposed ECC acquired higher EIC.