The Verification Of An IEEE1394 Bus Physical Layer Interface Circuit

Verification is time-consuming and complex in integrated circuit design process. It determines the schedule of a project directly and it is the key to project success. Due to the increasingly numerous and complex functions of ASIC chip, how to efficiently verify the chip has become a challenge of integrated circuit industry. This paper is based on the project in one company. The paper is to research the whole verification of an IEEE1394 bus physical layer interface circuit. The study has important practical value and significance for the development of IEEE bus physical layer with higher performance.Firstly, Chip-level functional verification technique is used for this topic after the fully analysis of verification techniques. A highly modular verification platform is designed based on the full understanding the functions of the IEEE 1394 bus physical layer interface circuit and related protocol. The platform is highly efficient because that the platform can be used to verify the transmitting function of a node and receiving function of the other node at the same time. Then, the grey-box verification method is applied to ensure that the functions of the interface circuit can be verified completely. The functions of the interface circuit are decomposed in detail and the efficient platform is used to verify the functions of the interface circuit. Post-simulating the functions of the interface circuit and comparing with the result of the pre-simulation are done to further ensure the correctness of the functions further. The verification of the IEEE bus physical layer interface circuit is completed in the topic. Functional verification results show that the functions of the IEEE 1394 bus physical interface circuit meet requirements of the technical indexes. Finally, chip testing scheme of the IEEE1394 bus physical layer interface circuit is analyzed. The overall test program is design, the idea of functional testing is introduced and the basic testing results of the performance parameters are analyzed.The properties that the efficient verification platform has can reduce verification period when studying IEEE1394 bus physical layer with higher performance. The verification method and testing scheme in the paper can be applied to verify and test other similar interface circuits.