The Design Of FAST Protocol Decoding To Accelerate Financial Process On The FPGA Platform

High-frequency trading has become popular since orders that reach the exchange earlier have larger potential of profit in financial markets. High-frequency trading principle is a kind of computer algorithm that buys or sells stocks in a short time. So the delay in electronic system of financial transaction is very significant. FAST protocol that compresses financial data to reduce bandwidth and time requirement of data transmission is one of the important technique backgrounds of High-frequency trading. FAST protocol hardware decoding is a modern research direction.The characteristics of FAST protocol are summarized in this paper, like the concept of template, stop bit, sequence and operator. The mask module, command module and decode module are designed so that this structure can fit 10 Gb network, parameterize FAST templates and decode concurrently.The performance is simulated on the SystemC platform and in RTL model. Repeating time of sequences and the number of sequences have larger impact on performance. It takes 21-72 cycles to decode FAST messages, and the longest latency is 3 times of the best. Then the structure is implemented on the ISE platform with Xilinx Kintex7 325-T devices. The maximum frequency is 250 MHz, which brings latency to 90ns-300 ns, which is lower than existing products and studies generally.