Geophysical Acquisition Node Equipment Design And Implementation

With the continuous development of geophysical exploration technology, detection equipment devices is toward the direction of a more accurate ADC, processing power of the CPU, as well as more advanced sensors upgrading, to acquire a higher fidelity, richer, and more clear seismic data. However, Currently the volume of acquisition devices are relatively large, upon detection of a wide range of geographic areas, the transmission cable length is limited by distance, not real-time processing and preservation of data, clock synchronization is difficult. This paper presents a distributed detection scheme, the use of GPS precision timing signals to synchronize the clock of each node device constituting a probe network. The GPS, ARM, FPGA, ADC integrated onto a board, consisting of an independent probe node, reducing the volume of equipment to carry. The node equipment use of internal power supply to the cable length limits, while using the powerful CPU to process data in real time and stored in the internal memory.This paper is divided into six parts:The first chapter briefly describes the current status quo and development trend of geophysical acquisition equipment, then studied in geophysics applications and related technical delegate when GPS accuracy.The second chapter introduces the overall design of the structure node geophysical equipment, including data transmission process design, hardware circuit hardware circuit of PCB component layout program, part of the data collection and data packets FPGA logic overall design, ARM part collecting data parsing and synchronization clock alignment analysis program overall design.The third chapter introduces the hardware circuit design of a geophysical equipment node, including the power supply design and component selection. As well as data acquisition and processing circuit design and related devices introduced. Analysis and data storage circuit design and related devices introduced. The paper then describes the design uses the ADC capture chip, Finally, the related design analog sources.The fourth chapter contains information on the FPGA hardware description language verilog and related development environment and simulation tool, Then introduced the ADC controller logic design,GPS data collection logic design, GPS timing signals and data aggregation module design, Finally, introduced the logical design of the double RAM ping-pong operations.The fifth chapter describes the background linux embedded systems as well as systems designed for this paper to compile Uboot, the kernel linux kernel and file system, and then introduces the acquisition interface design based on FPGA and ARM to communicate the necessary data, and collected data conversion and convert raw data file after the merger process based on GPS signals, and finally for the analog signal source systems used in the test program design.The sixth chapter is to test the performance of the actual circuit, analyze the data collected to test whether meet the requirements, at the same time multi-node test whether the data collected in the alignment calibration data synchronization PPS signal, Finally, this paper summarizes the work done and the prospects for future work.