A Research Of PCI-E Bus Based GPS Synchronized Clock Card

Time synchronization always has the vital role for system integration, with the PC bus has been upgraded from the traditional ISA bus and PCI bus to high-speed PCI-Express bus, in the past the GPS synchronous clock card design based on the two bus which according to the power system also need to be upgraded. This design aims to develop a GPS synchronization clock card which based on the new PCI-E bus, to provide accurate time for the intelligent equipment which used to record fault and record the event in the power automation system.Based on the characteristics of small batch data transmission and interrupt response of this card, the independent research and development CH367 of Nanjing Qin Heng company(WCH) has been selected as the PCI-E bus interface chip, for the cost of this chip to make the PC board is much more less than any other ways. In order to solve the problem of rate does not match which between the high-speed PC and low-speed microcontroller to access the dual port RAM, this design uses the new style parity page design patterns. This design also first use the double joint debugging method to debug the driver program, it greatly reduces the debugging time and at the same time reduces the difficulty of driver debugging.The design use the CH367 chip, STC microcontroller, dual port RAM, CPLD and other chips to complete the hardware circuit of the GPS synchronous clock card, to mainly realize the time decoding from IRIG-B pattern to 200 us precise time scale and write to dual port RAM and provide to the PC with the method of interrupt way or query way, to implement the absolute time scale information output pattern of RS-232, which is second, minute and hour three kinds of contact pulse output. And realize the date and time display function of the synchronization clock card, which expected that the time synchronization accuracy is less than 10 us. In order to make PC application program to operate this card, we designed driver program for this card, and used Windbg debugging tools to debug the driver program. In order to test the correctness of hardware design and driver program, a PC test software developed by VC6.0.During the test, we successfully read the GPS synchronization clock card dual port RAM in 200 us time scale use the query mode and interrupt mode through PCI-E bus, and set the time to the PC, with the time accuracy less than 10us; And capture the time information of the synchronous clock card which use the RS-232 pattern; Time and date shows the circuit can working normally.