Design And Implementation Of A Detecting Algorithm For Star Sensor Based On FPGA

Star sensor is a navigation equipment through capturing and processing star maps. High precision and no cumulative error makes it widely used on modern aerocraft. For navigation equipment, higher requirements should be met because of aerospace technology's development. To improve the processing rate and accuracy, studying the algorithm and the hardware structure is an import research subject of the star sensor.Star sensor depends on image processing algorithms, including pretreatment, centroid coordinates extraction and star identification. Star detection algorithm is used to extract the centroid coordinates, which is an important part of star sensor algorithm. The detection's accuracy, precision and processing rate have an obvious influence on star sensor performance. Algorithms for star images are of serial requirement, as mass data, high complexity, high performance of real-time and reliability. DSP(Digital Signal Processor) and FPGA(Field Programmable Gate Array) are widely used processors with high performance. The DSP+FPGA architecture is mainly used, with disadvantages including complex hardware system, large area of circuit, low utilization and low rate.This paper introduces the development of star sensor and algorithms in common use, it also describes a star detection system on a single FPGA. In this paper, star images features are analyzed and a few of characteristics are extracted for star detection. Squared centroid method is implemented with the help of SOPC(System on a Programmable Chip) technology. Algorithm design of star images and appropriate processing structure on FPGA are presented in details. A system is realized on a single FPGA, with function of pretreatment, star detection and centroid extraction. This system has smaller size, faster processing rate of tens to hundred fps, and 99.5% to 100% mission success rate for star identification test. The right ascension and declination's variance of test results is lower than 1.5 arc-second. The algorithm and hardware system has been tested and verified to have performance requirements met. The results are significant to practical applications.