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Design Of Pavement Crack Collection And Detection System Based On FPGA

Posted on:2017-06-09Degree:MasterType:Thesis
Country:ChinaCandidate:W GeFull Text:PDF
GTID:2322330482984838Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
Nowdays,the highway is still the main mode of transportation in the world,that's important to the economic development and people's live of a country. So the crack of the road to find and repair,which has become a large project. People have done a lot of research and design work on the pavement crack detection equipment, but the equipment is difficult to be popularized because of the high cost.In this paper, the design of pavement crack collection and detection system based on FPGA will integrate image acquisition, GPS positioning, image processing and others into a core board.It's the purpose of storing the image data,so that the whole system has a very good image acquisition accuracy,at and has the advantages of small size and low cost.The main contents of this paper include:1.The design of integrated board system based on FPGA. Respectively to design the corresponding drive timing, hardware connection principle and Verilog code of image mining function module, GPS positioning function module, cache function module constitute the integrated board system.2.The research and design of the bit level median filtering algorithm in image processing module and image edge detection Sobel algorithm module.Through the research and improvement of the original median filtering algorithm,the logic circuit design of and the Verliog code of bit level median filtering algorithm module is realized.On the basis of learning the mathematical principle of the Sobel algorithm and drawing lessons from the existing literature, the Verilog code design of the gradient operator of the Sobel algorithm is realized.3. The design of the pattern recognition. Using BP neural network algorithm to build a crack recognition classifier. Extracting the characteristic parameters of the crack binarization image by image projection;the training process of theclassifier is designed.
Keywords/Search Tags:FPGA, image processing, Verilog HDL, pattern recognition
PDF Full Text Request
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