The Design Of The Clock Generator Of 4GSPS Arbitrary Waveform Generator

As a signal source which is widely used in the field of electronic testing,arbitrary waveform generator consists of waveform synthesis module,output conditioning module,clock module,interface module,etc.The main function of clock module is to provide sampling clock for waveform synthesis process and synchronous each part in the process of waveform synthesis.This thesis researches on the clock module of “4GSPS arbitrary waveform generator”.In view of the requirements for sampling rate and channel timing skew of4 GSPS,it designed the clock module whose two-channel timing skew can be fine-tuned and whose precision of broadband can be varied.The main research content is as follows:1.Needs analysis of clock module.Aiming at the index requirements of 4GSPS arbitrary waveform generator project,and combining with waveform synthesis scheme,it confirmed the requirements of sampling clock,whose frequency range is 1GHz-2GHz,precision is ±1kHz,resolution ratio is 100 Hz,phase noise is better than-76dBc/Hz@10kHz when the output frequency is 2GHz,and output power is not more than 9dBm-15 dBm sampling clock requirements.Combining with the control scheme of channel timing skew precision,it determined the fine-tuned requirements of clock timing skew,whose range is-1ns to +1ns and whose resolution ratio is 10 ps.2.Schematic design of clock module.Aiming at the requirements for indicators related to the frequency of sampling clock,it studied modern frequency synthesis technology,and combining with high resolution ratio of DDS,fast switching speed and big output frequency range of PLL and other advantages,the clock generation scheme that DDS stipulates PLL and whose broadband precision is variable was designed;Aiming at the functional requirements that clock channel is independent or synchronous and external clock is selectable,the switching scheme of clock source was designed;Aiming at the index requirements of clock timing skew adjustment and through comparing several methods of timing skew adjustment,the scheme which uses delay line to adjust clock timing skew was designed.3.Hardware design of clock module.Combining with relevant indicators requirements of clock frequency and the scheme of clock generation that DDS stipulates PLL and whose broadband precision is variable,and choosing AD9912 and ADF4351 asthe core chips,the clock generation circuit was designed.Combining with the switching scheme of clock source and using analog switch and clock distribution chip,the switching circuit of clock source was designed.Combining the clock timing skew precision adjustment scheme and choosing SY100EP196 V as a delay unit,clock timing skew adjustment circuit was designed.4.Driver program design of clock module.According to the division of functions,it respectively analyzed the design process of driver program of clock generation,clock source switching and clock timing skew precision adjustment.After testing,the frequency range of output clock signal is 1GHz-2GHz;frequency accuracy is less than ±1kHz;resolution ratio is less than 100 Hz;phase noise when the output frequency is 2 GHz is better than-83dBc/Hz@10kHz;and output power range is11.16dBm-13.23 dBm.It can realize the switch of clock source,and the adjustable range of clock signal channel timing skew is greater than-1ns to +1ns,and the resolution ratio is 10 ps.All the indicators meet the requirements of the project.