Research Of ESD Protection And Design Of High-Efficiency DC-DC Converter With A Wide Load Range

With the rapid development of portable electric equipment,its power supply requests a better performance.Improving the efficiency of power management ICs is a key point.Furthermore,as the development of the semiconductor technology,electrostatic discharge(ESD)damage to ICs is more and more severe.During the design of the power management ICs,the whole chip ESD protection devices and circuits need to be studied to improve the ESD protective capacity.These ESD protection devices were designed and fabricated in a CSMC 0.5?m BCD process.A TCAD simulation software Silvaco was used to analyze these devices and compared with the result of the transmission line pulse(TLP)testing.The Smic 0.13?m CMOS process was used for the circuit simulation of DC-DC converter.The main content of this thesis include:1.The physical mechanism and the physical models were studied in device simulation of the ESD devices.The thesis analyzes the key parameters which make a great influence on the simulation results,including the impact of dosage concentration to the trigger voltage,the junction width to the holding voltage and the lifetime of carries to the holding voltage.Through the modification of the key parameters,the trigger voltage and the holding voltage of the simulation were adjusted based on the devices such as MOS and Silicon Controlled Rectifier(SCR).After the simulation of five devices which uses the same parameters,the relative errors were controlled less than 10%compared with the TLP testing results.Besides,four dual-direction SiliconControlled Rectifier(DDSCR)devices were predicted by using the physical models and key parameters obtained before,and were compared with the TLP testing results.2.The voltage-tolerance capacity and ESD robustness were improved by designing novel structure such as the improvement of the DDSCR and the guard ring layout structure.The Atlas simulation and TLP testing were used to analyze these devices.The test results show that the proposed devices are excellent for the higher secondary breakdown current and exhibit the stronger ESD robustness.3.In the research and design of a voltage-mode DC-DC buck converter,the PWM modulation mode was chose and the voltage converts from 3.3V to 1.2V with an operating frequency of 1MHz.The loop includes main circuit,error amplifier,ramp oscillator,PWM comparator,deadtime control and drive circuit,level switching circuit,current detection circuit and logic control circuit.4.A current detection circuit and a logic control circuit were added in the DC-DC converter,according to which ameliorate the issue of low efficiency under light load conditions.The transistors were automatically controlled and the number of transistors decreases when the output current decreases,so the power consumption was reduced and the efficiency was raised.The simulation results show that the proposed DC-DC converter has a wide range of the output current which is 20mA to 100mA,and the efficiency keeps more than 85%by splitting the transistors.