Research And Design Of A PCM Controlled Wide Input Range High Efficiency Synchronous Step-down Converter

With the vigorous development of the consumer electronics market,the demand for PMIC(Power Management Integrated Circuit)is getting stronger and stronger.At the same time,the upgrading of electronic equipment also puts forward higher requirements on the performance of PMIC.As a widely used step-down DC-DC structure,the BUCK converter is gradually developing towards the trend of wide voltage input range,high efficiency,and high power density.Therefore,choosing an appropriate system control method and circuit optimization measures plays an important role in improving the performance of the final chip.Firstly,several common control strategies of BUCK converters are analyzed and compared.Considering the design goals of wide input range and high efficiency,the peak current mode(PCM)with more balanced performance in all aspects is finally selected as the control method.For the sub-harmonic oscillation phenomenon when the duty cycle is greater than 0.5,the improved average model method is used to model the small signal.The loop transfer function with slope compensation is deduced,and the stability of the system is verified through Simplis.Then the system performance metrics and pin functions are defined,the functional block diagram is designed,and specific working process of the modules is briefly explained.In order to reduce the switching loss at light load,the pulse skip modulation(PSM)and sleep mode that can be selected through the external port are designed.To reduce the conduction loss as much as possible,the internal resistance of the power tube is compromised.Last but not least,in the face of unexpected situations such as high working temperature and internal power supply undervoltage,a corresponding abnormal protection circuit is designed to ensure the reliability of the system.Based on the 0.18μm BCD(50 V)process,the bandgap reference and pre-step-down circuit,error amplifier and its clamping circuit,slope compensation and high-speed peak current comparison circuit,zero-crossing and over-current detection circuit and protection circuit are designed and simulated on the Virtuoso platform.Finally,according to the application conditions,the parameters of peripheral passive devices are optimized to complete the systemlevel simulation.The results show that the output voltage ripple is below 7m V and stay stable when the input is 12 V and the output is 5V.When the input voltage jumps between a widerange of 5～42V,the error of the output voltage is kept below ±1.85%,the linear adjustment rate is below 0.1%/V,the recovery time is within 110μs,and the maximum load current can reach 3.5A.The maximum efficiency under typical application is 95%.The PSM and sleep mode are simulated when the load current is 15 m A and 150 m A,and the efficiencies are 64.18%and 84.65%,respectively,which is higher than the efficiency of PSM alone.Overall,it meets the design requirements of high energy conversion efficiency and high-precision output.At last,the layout design is completed,and the footprint of the chip is 1970μm×1580μm.