The Logic Design Of Time Triggred FC-AE-over-Ethernet Switch

In recent years,the avionics network has developed rapidly,and it is more and more important in the field of aerospace.Time-triggered network avoids data frame competition in the physical link,and provides strong real-time for the network.The avionics network has high requirements of real-time and reliability,and using the timetriggered network into the avionics network is a development trend.Fiber-based FC-AE technology has been applied to avionics networks.On one hand,the existing avionics network topology is complex,and many types of network are both based on the Fiber Channel FC-AE network,as well as Ethernet.On the other hand,the types of services that the avionics network needs to support include real-time control commands,sensor data,and non-real-time services.How to use a unified network architecture to support a variety of types of avionics business has become an urgent problem to solve.Existing FCAE network technology does not support time-triggered services,and existing TTE technology can not support FC-AE services.The time-triggered FC-AE-Over-Ethernet network architecture supports both FC-AE services and time-triggered services.It lets a unified network architecture to support multiple types of avionics.The main work of this thesis is as follows1、The thesis design a 32-port FPGA-based time-triggered FC-AE-Over-Ethernet switch based on FPGA,which is divided into two non-interference pairs of TT switching module and FC-AE-Over-Ethernet switching module.This design can forward the TT message according to the time schedule configured by software,and send and receive ordinary Ethernet data frame and FC-AE-Over-Ethernet protocol data frame.2、Based on the SAE AS6802 protocol,a time synchronization module is designed and analyzed to realize the different methods of network time synchronization.The method is implemented entirely by hardware,and the synchronization process does not require software,which can achieve very high synchronization accuracy.3、It changes the exchange structure,and use a set of parallel FIFO to replace the original FIFO queue to store information of frame,which can avoid the blocking phenomenon.At the same time,it uses RAM to replace the traditional FIFO storage,and uses virtual VOQ queue to store information.It saves the wiring,storage resources,and improves the performance of the switch effectively.At the end of this thesis,the simulation platform is constructed by using the simulation tool named modelsim,and change the logic of the design according to the simulation results.after getting through the simulation,we construct the test environment and make board tests,to verify the function of the switch.