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Software Verification For VLSI Implementation Of On-board Image Compression Kernel

Posted on:2018-03-31Degree:MasterType:Thesis
Country:ChinaCandidate:W J ZhouFull Text:PDF
GTID:2322330515459902Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
With the successful launching of Chang'e 3 satellite,Dark Matter Particle Explorer satellite and the Quantum Experiments satellite,China has made a tremendous breakthrough in astronautical and space exploration technology.At the same time,the technology of spaceborne imaging has obtained a rapid development.The resolution of on-board image is getting higher,and the amount of data increases more gradually.Mass image brings tremendous pressure on image processing,satellite storage capacity and transmission bandwidth.Therefore,the research of real-time and efficient onboard image compression is critical.The Consultative Committee for Space Data System proposed a recommended standard CCSDS 122.0-B-1 for image data compression in November 2005 which has high performance,low implementation complexity,and occupies small amount of resources.This standard used on satellite are usually implemented on ASIC or FPGA.The development of hardware-based systems is time-consuming,and the cost is high.In order to assist in hardware development,and to reduce the cost of time and resources,a software verification system for VLSI's implementation of CCSDS-IDC algorithm is proposed in this paper,which is developed by C and C++.This system not only realizes the CCSDS-IDC algorithm,but also has the inquiring function of compression parameters and the internal data.In addition,through in-depth analysis of the CCSDS-IDC algorithm,a novel optimized hardware parallel implementation is proposed in this paper and the software verification is provided.Experimental results show that the occupied resources of the improved software system can be reduced to 33.3%,with the processing time increased by 16.1%~23%,compared to that of the existing parallel implementations.Therefore,this implementation can save the hardware resources efficiently.This paper is arranged as follows: The first chapter will introduce the research background,goals and significance,as well as research contents;Chapter II will present a review of CCSDS-IDC algorithm and the relevant theory;Then in Chapter III,the design of software verification systems of onboard image compression kernel will be detailed and the proposed hardware implementation will be described;The fourth chapter will interpret the results of the verification system and the performance of the optimized implementation;Finally,Chapter V will summarize this paper.
Keywords/Search Tags:CCSDS-IDC, Wavelet Transformation, Bit Plane Encoder, Software Verification, GUI
PDF Full Text Request
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