Design And FPGA Implementation Of Baseband For Short-time Burst Communication System

In the military communication exists a variety of interference,it has a great challenge to send and receive data correctly.Burst communication has the characteristics of short signal transmission time and uncertain information sending time,which makes it difficult to capture the spectrum information of the signal and avoid human malicious interference.It can be used as a common communication method in the military field.Basing on "xxxx system",the purpose of this project is to develop a fast transmission of information within a low bandwidth,and realize short-time bursts of communication.The thesis research on the base-band of the communication system,and designs the frame structure of the short burst communication,as to the error performance of the low-density parity-check code is close to the Shannon limit as the channel coding scheme,taking a constant envelope of the GMSK modulation.According to the theoretical research and design,the design of the baseband part is implemented in FPGA using Verilog language.The design method,implementation process and simulation results of the main module is given in this thesis.The main contributions of this thesis are as follows:1.According to the characteristics of short burst communication,the thesis designs a frame data structure with high data transmission efficiency,which consists of synchronization sequence and data frame.The frame synchronization method of distributed method is proposed.The distributed symbol synchronization sequence has the function of timing synchronization and frame synchronization,and reduces the false alarm rate of frame synchronization.For the frame structure,the thesis takes the corresponding system synchronization program.2.Based on the characteristics of the LDPC matrix with a fixed structure,LDPC codes adopt a fixed logic structure to implement the coding algorithm,which avoids the iterative process.And in the decoding process,an improved minimum decoding algorithm is adopted,reducing the FPGA resource consumption.3.The one-bit differential demodulation of GMSK requires a large amount of storage resources to be used for division and tangent operation,so demodulation is performed using phase difference.And according to the characteristics of its pre-filter coefficients,the filter algorithm is optimized,further reducing the consumption of FPGA storage resources.4.In the signal detection and synchronization module,the correlation peak capture operation consumes a large amount of FPGA resources.In this thesis the structure of the multiply accumulator is optimized to reduce the use of logical resources.