The Design And Implementation Of DSRC Protocol Baseband Circuits In ETC System

With the development of road traffic,road congestion has become the main problem in the society today.Intelligent Transportation System(ITS)is the main solution to solve road congestion.Among them,Electronic Toll Collection(ETC)has become an important method to solve road congestion.Dedicated Short Range Communication(DSRC)baseband circuit is an important part of the ETC chip.DSRC connected to the MCU and radio frequency unit,mainly achieves after the decoding of the data processing.Baseband circuit mainly includes sending and receiving circuit,codec circuit and wake-up circuit four modules.In 2007,the State formulated the corresponding national standard on short-range communications for electronic tolls,with the aim of regulating the development of domestic related industries.The release of national standards has played a significant role in promoting the popularity of the ETC system.In recent years,with the national high-speed development,the previous national standards have been less suited to the rapid development of traffic construction.As a result,a new generation of ETC system chips will soon be used in the development of traffic roads.This paper firstly analyzes and expounds the national standard in detail,and then analyzes the encapsulation method of the frame structure and the specific information bits of the fixed effective information frame by analyzing the relevant data link layer information in the communication protocol.To meet the actual requirements of the chip design requirements,the proposed in this design,mainly to reduce the baseband circuit power consumption as the main design indicators.Reduce the power consumption process from the system layer to the circuit level,the entire chip power consumption to optimize the problem.In the DSRC communication protocol circuit,the wake-up circuit is from the system level to the ETC system chip power optimization,wake-up circuit is in working condition,ETC system,other circuits are in the off or sleep state,after receiving the wake-up enable signal,The MCU feedbacks the corresponding enable signal so that the transmit and receive links are able to function properly.At the circuit level,the characteristics of different circuit modules,using gated clock method,the DSRC communication protocol standard in the main circuit module power optimization.Finally,compared with the actual chip used in the current mainstream market,the ETC chip designed in this paper has a 15% reduction in power consumption and a 10% savings in chip area.The entire chip DSRC communication protocol baseband circuit design mainly uses the "topdown" design method,the various modules to a reasonable division.The Verilog circuit language is used to implement the design of the baseband circuit.For FM0 codec module,using tsmc 0.18 um schematic diagram for circuit design work.And then the function of the circuit verification work,and finally use tsmc 0.18 um process DSRC baseband circuit backend layout design work.