Research And Design Of A Radiation Hardened Phase-Locked Loop

Along with the rapid development of aerospace technology, the activities of human exploring space become more and more frequently, which increasingly improved the requirement of reliability and stability of the electronic equipment on the spacecraft. Phase-locked loops(PLLs) are widely applied in frequency synthesizer and clock generator, which is a core component of the spacecraft electronic system. The PLLs working in radiation environment are facing threaten of the single-event transient(SET) when the energetic particle strike a sensitive node. The SET maybe cause serious effects on the PLL lead to phase and frequency drift, resulting in the incorrect data send by the spacecraft. In order to improve the reliability of the PLL in radiation environment, a radiation hardened by design(RHBD) PLL is researched and designed in this thesis. This thesis including:Firstly, an unhardened reference phase-lock loop is designed to analyze the SET sensibility of the PLL. Adopting the low voltage cascade technology and difference switch to modify the traditional charge pump(CP), successfully reduced the non-ideal effects of the CP. Using differential delay unit with a PMOS symmetric load, achieving a wide range frequency voltage-controlled oscillator(VCO) with a high rejection to noise of supply and ground. Simulation results show that the rate of current mismatch of charge pump is only 0.6% in the range of 0.4V to 1.3V. The output frequency range of the designed PLL is between 90 MHz and 2275 MHz with a 1.18 GHz center frequency operation. Under a 62.5MHz input frequency, the PLL can enter lock-in state within 1.336μs.Secondly, a double-exponential current model was joined into the PLL circuit to simulate and analyze the SET in each key sub-circuit. Based on the data of different operation frequency, different strike energy, different strike node, this thesis find that the output stage of CP and VCO are sensitive to SET, the effect of SET in phase detector and divider is insignificant, which can be ignored.Finally, a radiation hardened by design CP and a radiation hardened by design VCO are designed. Based on detection and compensation idea, the thesis amends a fast current compensation technology to improve the inhibiting capacity of SET. With the triple module redundancy technique, the VCO has been eliminated the SET susceptibility. Annular layout and guard ring is used to improve radiation hardness ability for PLL. The final simulation results indicate that the designed hardened PLL has a 1.336μs lock-in time under the 1GHz operation frequency, a 48.5% duty cycle. Compared with the unhardened PLL, the disturbance of control voltage has a 93.8% descent, a 71.5% improvement in recovery time, a 91.9% improvement in maximum phase shift. In conclusion, the designed radiation hardened PLL has well improved the reliability of PLL in radiation environment.