Research On Radiation-Hardened-by-Design Techniques For DC Bias Circuits In 28nm CMOS Process

Microelectronic circuits and systems in spacecraft are facing the threat from radiation environment.With the continuous reduction of process size and the sharp increase of circuit scale,the generation and propagation of single-event transient(SET)become more complex,which seriously threatens the normal operation of nano CMOS integrated circuits.As an important branch of analog circuits,DC bias circuits are widely used in analog and mixed-signal systems.Compared with the digital circuit working in binary"0"or"1"state,the DC bias circuit provides static DC voltage or current for analog and mixed-signal circuit design.Therefore,once heavy-ion hits on the key node of the DC bias circuit,the disturbance caused by radiation can cause a wide range of global effects in the whole IC,resulting in signal errors and function interruption,seriously threatening the normal operation of the system.Therefore,radiation-hardening technique for DC bias circuit in advanced CMOS process is a key problem to be solved.This paper studies DC bias circuits in 28 nm CMOS process,in conjunction with theoretical analysis,TCAD simulation,laser radiation measurement,and heavy-ion radiation measurement as research methods,systematically studying the charge collection mechanism and radiation-hardened-by-design(RHBD)techniques in DC bias circuits.SET mechanisms,transistor-level RHBD techniques,circuit-level RHBD techniques,and module-level RHBD techniques are proposed in this paper.The main work and innovations of this paper are as follows:(1)In the aspect of SET mechanism analysis,the charge sharing and pulse quenching effect between adjacent stages of analog circuit is systematically studied in this paper.Through simulation,it is found that there is an optimal space between adjacent stages of analog circuit in 28 nm bulk CMOS process.A complete suppression of single-event disturbance can be realized through pulse quenching effect.The simulation results indicate that,if the adjacent stages of the analog circuit are too close,although the disturbance caused by the hit node is effectively mitigated by pulse quenching effect,the charge collected by the passive stage plays an adverse role at the output of the circuit.This paper proposed that the charge sharing and pulse quenching effect plays a dual role in the SET alleviation in analog circuits.This paper provides a new idea for layout-level RHBD technique.(2)In terms of transistor-level RHBD techniques,this paper proposed that MOS devices with body and source connected together(BTS technique)can effectively mitigate the SET-induced disturbance in analog circuits.BTS technique has been successfully applied in operational amplifier for SET mitigation.Simulation results indicate that SET pulse amplitude is reduced by 26.4%with SET pulse-width reduced by75.8%when heavy-ion hits with LET of 30 Me V?cm~2/mg.Meanwhile,BTS technique can also be applied in digital circuits for SET mitigation.Heavy-ion experiments show that the cross-sections of the circuits in BTS configuration are reduced by at least 45%.(3)In terms of transistor-level and circuit-level RHBD techniques,current mirror circuit is studied in this paper.At the transistor-level,the current mirror transistors are in dynamic threshold-voltage MOSFET(DTMOS)configuration,that is,the body and gate of multiple transistors are connected together to realize the transistor-level radiation-hardening of the current mirror.Simulation results indicate that DTMOS technology can effectively mitigate the output disturbance induced by SET in cascode current mirror.At the circuit-level,an additional charge dissipation transistor is added to achieve SET mitigation.This technique consists of two inverters and a dissipation transistor.As a particle hits on circuit,the inverter turns on the dissipation transistor to dissipate collected charges at the sensitive node.Simulation results indicate that the SET pulse-width is reduced by 48.4%with LET of 30 Me V?cm~2/mg.(4)In terms of module-level RHBD techniques,this paper proposed two methods for SET mitigation in bandgap circuits.In the first RHBD technique,an automatic error detection and isolation technique is proposed,which combining with dual-mode redundancy can completely eliminate the output disturbance caused by SET strike.This technique can be widely used for radiation-hardening in DC circuits.Regardless of the bandgap reference architectures and the output DC voltages,the proposed technique can reduce the SET-induced disturbance to a negligible level.In the second RHBD technique,an error signal filtering technique is proposed,which converts the SET pulse into high-frequency error signal,and then filters it through the on-chip filter.This technique reduces SET amplitude without introducing excessive area overhead.(5)The proposed DC bias circuit RHBD techniques are applied to high-speed mixed-signal systems.In this paper,a 16 Gbps clock-data recovery(CDR)circuit in the serializer and deserializer(Ser Des)system is taken as an example to study the impact of RHBD techniques in DC bias circuits on complex mixed-signal systems.Test chips were designed and tape-out under 28 nm process for comparison.Laser irradiation experiments indicate that the RHBD techniques proposed above in DC bias circuits can significantly enhance the robustness and radiation performance of high-speed mixed-signal system.Finally,we give the prospection of the unfinished works and future researches in nano CMOS DC bias circuits for radiation-hardening design.