Research On IRIG-B Multi-Timing-Source Timing System Based On CPLD Devices

With the development of defense and information technology in China, requirements on new types of timing system devices for distributed measure & control shooting range is becoming more and more strong. O n one hand, the time synchronous precise of timing system is required much more higher. O n the other hand, the timing sources for timing system is also asked to be redundancy with different types o f system supports. Therefore, it is becoming a challenge for timing system architecture design on measure & control tests in current shooting range. U nder backgro und o f suc h co nd it io n, t he researc h o n new t ype o f I RIG- B multi- timing-source timing system is projected. And basing on the analysis of functions and design standards in mission paper approved, a set of technical solution based on CPLD technique for high precision timing system is brought forward.Firstly, the overall design solution which takes CPLD and ARM as center processing unit is brought forward in this paper. And followed with the selecting solution on electric components of the system, the system hardware design solution is presented with detailed electric circuit design skills listed up. Then, the system development environment and the design of software working mode is discussed and presented. And the overall software solution is presented, which includes design scheme of ARM main program, design scheme of CPLD logics, design scheme of GPS/BD2 communication protocol parse programs, design scheme of power- fail protection program, analysis on system real time ability and design scheme of interrupt service program, etc.The CPLD logic circuit design solution for IRIG- B timing code is presented in chapter 3. In detail, with the help of analysis on IRIG-B timing code specifications, the CPLD logic circuit design solutions for IRIG-B(DC) encoding, IRIG-B(DC) decoding, and modulation output control on IRIG-B(AC) timing code are presented one by one, with detailed programming process listed.The CPLD logic circuit design solution for checking working state of timing-source is presented in chapter 4. Taking different working characters of timing sources in the system into consideration, two types of checking methods are presented in detail, which is named as character signal test and character content test respectively.Consequently, the test results of timing system device make in this paper shows that all functions presented in system mission paper are finished. And the timing alignment error of digital timing code is less than 10 ns, which can reach related precision standard requirement.