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The Design And Implementation Of ADS-B Receiver

Posted on:2018-03-10Degree:MasterType:Thesis
Country:ChinaCandidate:D Y LiuFull Text:PDF
GTID:2322330533960080Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Automatic Dependent Surveillance Broadcast(ADS-B)System is an aircraft operational surveillance technology,which is based on the Global Navigation Satellite System(GNSS).And the system is depended on air-to-air and air-to-ground data link to transform.It is regarded as a main surveillance mean and part of the Communications,Navigation,Surveillance / Air Traffic Management(CNS/ATM)which is defined by the International Civil Aviation Organization.In recent years,varieties of nations such as America,Australia and China have published many relevant policies to put ADS-B technology into use.Three data links can be used for ADS-B which are 1090 MHz Mode-S Extended Squitter(1090ES),Universal Access Transceiver(UAT)and VHF Digital Link(VDL)Mode 4.In China,most of the aircrafts use the 1090 ES,so the type of ADS-B receiver we design is based on it.The main contents are as follows:Firstly,the thesis introduces the development and the present application situations around the world of the ADS-B system and ADS-B receiver.Secondly,in the case of the structure of the ADS-B receiving system,the thesis gives the principle design of ADS-B receiver based on the synthesis analysis for the ADS-B receiving system.The main contents of the design are as follows: Preamble Detection,Bits and Confidence judgement,Error detection and correction,Message decoder.Thirdly,in order to familiarize with the implantation process of the hardware ADS-B receiver,the design of software receiver based on C is given.Also,fix-pointed process is finished to the software receiver.The message decoder module is shared by the software receiver and the hardware receiver.Fourthly,based on the software receiver,the design of the hardware receiver based on FPGA is given.In the case of the different data processing,some blocks are adjusted and improved to adapt to the FPGA situation.Also,the improved blocks in FPGA need less hardware consumptions.Fifthly,the system performance testing is finished to the hardware receiver.Results of the testing show that the performance of the receiver is met the requirements of the DO-260 B standard for ADS-B and the receiver is feasible.
Keywords/Search Tags:ADS-B, 1090ES, software receiver, FPGA, hardware receiver, Message Decoder
PDF Full Text Request
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