Study And Design Of Dynamic Bias And Transient-Enhanced LDO

With the development of the Internet,portable devices,smart home electronics industry to flourish,the new electronics industry to power management chip research into a new hot spot.Smart chip internal,such as multi-channel LED driver,USB-Type-C power management chip,high-performance ADC / DAC often have complex digital circuits.In order to take into account the size and performance,digital circuit operating voltage is generally lower than the analog circuit,and the digital module of the frequent switching action will bring greater noise to the power supply,digital-analog mixed-chip digital module needs a separate power supply.Low Dropout Linear Regulator(LDO)is the most critical power module for on-chip power system solutions featuring low noise,high accuracy,and small area.The future development of the Internet of things,the trend of intelligent chips,making digital-analog IC internal digital module becomes more and more important and important.Digital-to-analog mixed-signal digital module is characterized by low noise and ripple requirements,but the transient and area requirements,so a fast transient response of the external compensation LDO is very important.Aiming at the requirements of fast transient response,low dropout voltage and small area of digital power supply driven by high-performance digital-analog mixed-signal chip,a transient enhanced NMOS LDO regulator is studied in this paper.The main work can be summarized as follows:(1)A high-order compensation Bandgap circuit is proposed.This circuit is based on the exponential relationship between current gain and temperature of the NPN transistor and the subthreshold region IV characteristic of the MOS transistor.(2)A novel adaptive charge pump circuit is proposed.The charge pump clock is provided by a low-power adaptive oscillator that adjusts the clock frequency according to the input voltage and load,making the charge pump output voltage stable at a set value.(3)A novel LDO transient enhancement circuit is proposed.The circuit is composed of a transient-enhanced comparator and a capacitive-coupling structure.The transient-enhanced comparator directly controls the tail current of the error amplifier through the coupling capacitor,so that the transient enhancement circuit can respond quickly to increase the error amplifier Tail current,and the first op amp op amp error amplifier to form a push-pull structure to quickly reduce the LDO transfer transistor gate voltage,making the output voltage overshoot be quickly inhibited.(4)Combining the above mentioned three high-performance circuits,a novel dual-loop push-pull transient-enhanced LDO solution with high accuracy and high efficiency is realized.The proposed LDO was designed and verified by a 130 nm BCD process.The results show that the maximum undershoot is 39 mV,the maximum overshoot is 56 mV and the settling time is less than 300 ns when the loadtransient between 0.5mA and 100 mA.LDO overall static power consumption is 39?A,1KHz power supply rejection is-101 dB.