A Low Power Transient Enhanced Off-Chip Capacitor-free LDO Design

Low-Dropout Linear regulator(LDO)can provide stable,almost ripple-free output voltage.At the same time,because of its simple structure,low output noise,good voltage regulation and fast transient response performance,etc.It plays a pivotal role in modern power management units.Nowadays,electronic products are moving towards integration,so most researches in recent years have focused on off-chip capacitor-free LDO applied to System-on-Chip(So C)solutions.The two major difficulties of stability and transient characteristics of LDO designs without off-chip capacitor are current research hotspots.This article designs a low power transient enhanced off-chip Capacitor-free LDO for two major difficulties.Because there is no off-chip capacitor,this paper uses buffer frequency compensation circuit and miller compensation to compensate the system stability.The buffer stage frequency compensation circuit as the intermediate stage of the error amplifier and the pass tube can not only reduce the load of the error amplifier,but also drive the pass tube to improve the transient response characteristics.Due to the characteristics of low output impedance,the buffer stage can push the gate pole of the Pass tube to high frequency,thus making the system more stable.At the same time,the buffer stage also improves the slew rate at the gate end of the Pass tube,which improves the response speed of the LDO to a certain extent.A transient enhancement circuit is added to the gate of the Pass tube,This circuit improves the transient performance of the LDO during load transitions.A positive transient detection(PTD)circuit is added to the output.This circuit can significantly attenuate the voltage spikes caused by the steep load drop and reduce the amount of overshoot voltage generated during the transient response process.Due to the above-mentioned frequency compensation and transient enhancement measures,the error amplifier uses a first-stage transconductance operational amplifier structure,and uses a smaller bias current to obtain sufficient gain,while achieving low power consumption.Low power transient enhanced LDO circuit with low power consumption and external design based on Hua Hong Grace’s 0.11μm 5.5V CMOS process.The power supply voltage range is 1.8V-5V,the output voltage is 1.6V,the system can be stable within a load range of 50μA-100 m A.When the load current jumps at 99 m A/μs,the maximum overshoot voltage is 85 m V,the maximum undershoot voltage is 92 m V,and the recovery stabilization time is 4.73μs.Under no-load conditions,the system current consumption is about 66μA,while under a load of 100 m A at full load,the power consumption of the system is 67μA.