Key Techniques For Fast Instruction Set Simulator

Instruction Set Simulator is some kind of software simulating environment that particularly is developed for the micro processors of embedded systems. Instruction Set Simulator could describe the whole computer architecture including CPU,registers, caches and memory system by using programming languages. Instruction Set Simulators not only undertakes the function validity work in system level validation, but also is used as micro processors' architecture assessment tool and the applications' debugging tool per tape out. The simulation speed is the most important factor that restricts the current Instruction Set Simulator's application range.In order to fit in with IME-Diamond DSP embedded system development's demands for fast simulation speed of Instruction Set Simulator, this paper proposes an improved multi-core Instruction Set simulation technique which is based on existing static multi-core Instruction Set Simulator. The main tasks of this paper include: on the premise of not spending extra time, the simulating mode has been raised from single working mode to two different types of simulation: dynamic simulating mode and dynamic library function mode, and the Instruction Set Simulator can change simulating mode according to current simulating situation. Dynamic decode cache has been introduced in instruction decode phrase during dynamic simulating mode, and the operation code and operand of the current simulating instruction would be saved in the decode cache to avoid repeated decode. Instruction Set Simulator has been expanded from single thread working to multi-thread parallel execution. The newly increased sub thread is found by master thread at the beginning of simulating and works parallelly with master thread, which is responsible for analyzing the instruction contents of simulating machine code file, generating corresponding C functions for those instruction blocks that meeting with translation conditions, while the generated C function would be compiled into dynamic library functions which is used for master thread at dynamic simulating mode. In this way, the single instruction simulation could be replaced by instruction blocks' simulation, which could save the decode and execute cost of single instructions.The Instruction Set Simulator optimization technique proposed in this paper has been applied in IME-Diamond multi-core DSP processor 's software simulating environment--multi-core optimized simulator's development. Under the buildingsoftware test platform, using actual application function to prove the functional correctness and simulation performance, the experiment results show that this technique can improve the simulation speed indeed. The simulation speed of multi-core optimization simulator increases by about 20% compared to the existing simulators, and the average simulation speed is about 7 mips(million instruction per second), which is helpful to embedded system's development.