A Configurable Hardware Implementation Method For Hopfield Neural Network Based On FPGA

Associative memory is an important function of the biological brains. The Hopfield artificial neural network, which was proposed by Professor Hopfield in 1982, is a single layer fully connected feedback network, and is widely used in the simulation and research for associative memory function of the brain.Computer software simulation is usually taken as a general method for the realization and application of the Hopfield network. However this method cannot take full advantage of the characteristics of neural network, such as parallel processing, distributed storage, high self-adaptive ability and strong robustness. Therefore, the hardware implementation of the Hopfield neural network has become a research focus.At present, in order to realize the large-scale Hopfield network, the hardware implementation method is mainly based on very large scale integrated circuit(VLSI) technology, including using analog circuits, digital circuits, or analog/digital mixed circuits design technology. Recently, the implementation method based on FPGA has become a main method for the hardware implementation of Hopfield network due to the characteristics of convenience, reasonable price and flexible design. Nevertheless most of the existing hardware implementation methods are for a specific application with fixed scale network structure. On the other hands, in order to simplify the design process and reduce the design difficulty, fixed-point number algorithm is adopted, which makes the Hopfield network absence of generality, flexibility and difficult to achieve high performance. Therefore, it is urgent to get a common hardware implementation method based on FPGA for the Hopfield neural network, which can change the scale of the network and the operational precision according to requirements.A configurable modularization hardware implementation method for the Hopfield neural network based on FPGA is proposed. First of all, Modularization is applied to the Hopfield neural network model according to the overall operation process; Secondly, each module is digitized with Hardware Description Language(HDL) to form a general hardware implementation function module library; Finally, the desired Hopfield neural network hardware can be constructed according to practical applications, by combing all the demanded modules. Since the modules can be configured by setting generic parameters, the scale of the network, the multiplier/accumulator numbers of the neuron operation and the data width are to be changed flexibly by passing generic parameters.In order to verify the validity of the method, the Hopfield neural network hardware testing system for digital identification was constructed by combining MATLAB and FPGA. Experimental results show that the proposed hardware implementation method of the Hopfield neural network has the ability to flexibly configure the scale of the network, and also has the ability to adjust the resources occupied and the speed of operation according to the practical application. The test results of the system running speed show that the hardware implementation of the Hopfield network has higher running speed than software simulation and suits for high-speed, intelligent information processing system application requirements.This research provides a new method for the advanced application of the Hopfield neural network, and it can also provide valuable reference for other types of artificial neural network hardware implementation.