Desgin And Implementation Of The Verification Platform Of The Radar Signal Processor Based On Zynq

With the rapid development of semiconductor manufacturing technology and manufacturing technique, the integrated circuit has entered the era of So C which is based on the reusable IP. More and more functions are integrated into the So C. With the increasing complexity and design scale of So C, the difficulty of the verification is highlighted. In order to verfiy So C adequately, the work of verification occupies 50-70% of the development cycle of So C design, which has become the bottleneck of the complex So C design. Due to the verification is applied to the whole process of the chip development, it is becoming more and more important to verify the design sufficiently with the reasonable and efficient verification methods.PD radar signal processor is the core of radar system. Its parameters can be configured. It has complex structure and needs to process large amount of data. The PD radar signal processor includes three key IP cores, that is, DDC module, PC module and MTD module. It is a difficulty that how to carry on comprehensive verification effectively. First of all, the current popular So C verification technology were studied. The software and hardware coverification method and the modeling method of the executable models of processor and IP core were further studied. Secondly, according to the system structure of the radar signal processor and the functions that needed to be verified, based on the advantages of the ARM+FPGA system structure of Zynq, the modeling method of software and hardware coverification platform is determined. The processor was modeled through the actual processor chip and the IP core was modeled by FPGA prototype. Finally, according to the verification platform modeling methods, this thesis puts forward the hierarchical design scheme of verification platform which was based on Zynq. The application layer, system layer, drive layer, hardware interface layer and DUV layer of verification platform are implemented on the Zedborad development board of Zynq series. Among them, the application layer, system layer and drive layer were implemented based on the Processor System of Zedboard, while the hardware interface layer and DUV layer were implemented based on the Programmable Logic part of Zedboard. This verification platform provides a easily observable, hierarchical and efficient verification environment for PD radar signal processor.This thesis has verified the functions of the key IP core and whole system of the PD radar signal processor by using the constructed verification platform. Firstly, the DDC module was added to the verification platform. Compared with the response of standard reference model, the relative error of the DDC module is approximately 10-4. Secondly, PC module and MTD module was verified with a variety of configuration respectively. Compared with the standard models, the relative error of them were approximately 10-4. Finally, in order to verify interface timing and overall function of the key IP cores of the PD radar signal processor, the thesis verified the whole radar signal processor with a variety of parameters configuration. The relative error of the whole response is approximately 10-4, which indicates the correct function of the PD radar signal processor.