| Power amplifier is the last stage of a transmitter. At the same time, as the power amplifier needs to amplify and transmit the signal, it consume a lot of energy. For the two reason mentioned before, the performance of a power amplifier directly influences the entire communication system, such as the efficiency, linearity, stability and other properties of the performance. As a result, the optimization and improvement of the power amplifier has been the focus for the several recent years.In this thesis, a power amplifier of high efficiency and high linearity is designed. It is completed with the smic 0.18μm CMOS process. The power amplifier uses a two-stage amplifier cascade structure, using the envelope feedback loop to improve the linearity of the power amplifier. As a result, the power amplifier has a strong inhibitory effect to the white noise and interference of the input signal and also has a stable output. In this thesis, the performance of the power amplifier is tested in the Cadence software. The envelope tracking technology is also used to dynamically adjust the supply terminal voltage, reducing the power consumption when the amplifier works. As a result, the efficiency of the power amplifier is improved. The output mode is divided into three, controlled by the digital control module. Under the condition of-10dBm input signal amplitude, the output signal amplitude can be -20dBm, -5dBm or 10dBm, plus or minus no more than 1 dBm.In the end of the implement, the performance of the amplifier is tested with the sortware named cadence. The amplifier operates from a 1.8V power supply. The final test result shows that the when the input frequency is set to 433MHz and under-lOdBm input amplitude conditions, power amplifier efficiency can reach 28% or more, third-order output intercept point is about 23dBm. After testing the chip, this paper designs power amplifier can be used at a frequency of 433MHz RF transceiver chip, and has a high efficiency and linearity. |
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