A Design Of Routerfor Network On Chip

Continuing advances in semiconductor technology, have led to an industry-wide shift in focus towards modular designs that leverage parallelism in order to meet performance goals. Network-on-Chip (NoC) are widely regarded as a promising approach for addressing the communication challenges associated with future Chip Multi-Processors (CMPs) in the face of further increases in integration density. The promising Network-on-Chip is one effective solution to resolve the problem of conventional shared bus such as increasing power consumption, the limitation of bandwidth and data block.NoCs are embodied by a set of routers that are connected to each other and their main function selects the path that a given packet must take from its source to its destination endpoint. The performance of router directly impacts the NoC performance. However, the existing baseline router cannot fully optimize the potential performance. The research of router plays an important role on improving the performance of NoCs.Firstly, this paper do some research about the topological structure of NoC and the structure of routers. The routing computation and channel allocation infect the delay and throughput, a good routing algorithm can avoid the blocking of packets, efficient channel allocation can effectively improve the throughput of data packets. This paper makes an optimization based on the above five steps. Design a highly efficient network interface based on AHB protocol used to package data and unpack data; The virtual channel technology to effectively use the buffer space; Design the fault-tolerant routing algorithm to avoid the blocking of packets; On the basis of the study of traditional separatable allocator this paper proposed the matrix-diagonal virtual channel allocator and switch allocator. Finally, we carried out simulation and performance evaluation. By the Design Compiler, the clock frequency can reach 333MHz. By the software simulation and FPGA verification, we proved that the function of the router is correct. We compared the proposed router with the traditional and combinated router in the aspect of performance.The proposed router in the matching rate is significantly higher than traditional routers and 7% higher than the combinated router in the aspect of throughput. The throughput of router can reach 40flits/cycles. In case of high injectiong rate, the packet lantency of NoC based on our proposed router is lower 10% than the other two programs. The proposed router has obvious adbantages on matching rate, throughput and packet lantency. It can meet the goal of high performance for the NoC and suitable for a variety of NoCs based on different topology. The paper can provide reference for the research of Network-on-Chip and CMPs.