Channel Codec Algorithm Research And Realization

Communication system will be subject to interference multiplicative and additive noise and deformed in the communication process, making detection receiver error. On the transmitting side signal is encoded in order to increase the degree of redundancy, is used at the receiving end decoding method for signal reception method can effectively reduce the error rate of the received signal, to ensure the reliability of signal transmission. In this paper, a method for encoding and decoding RS codes, coding and decoding convolution codes, RS codes and concatenated convolutional codes has been studied and implemented mainly as follows:First, an improved decoding algorithm for RS codes. On the basis of the principles introduced RS code encoding and decoding algorithms, to existing Chase 2 decoding method is improved, reducing the number of elements in the original sequence set tentative algorithm; Simulation results show that the improved algorithm performance slightly on the basis of loss greatly reduces the computational complexity. In addition, the paper also visible light communication RS codes in additive white Gaussian noise channel, the actual measured under (VLC) channel, the BER performance simulation under different conditions of redundancy.Second, respectively, under ideal Gaussian white noise channel and Found VLC channel conditions, the simulation constraint length of the convolutional code encoding and decoding depth retrospective impact of these two different values of the parameters on the error rate performance, in addition to the ideal channel simulation of BER performance of Turbo code decoding algorithm at different times and different iterations, and with the performance of a convolutional code is simulated comparison.Third, the simulation analysis of the visible channel at channel RS code and convolutional code concatenated coding error rate performance. In additive white gaussian noise channel for RS code and convolutional code concatenated coding system, simulation of different maximum number of symbols in the RS error correction code, convolution code system BER performance under different constraint length.Fourth, the RS code, convolutional code and their serial concatenated coding, write the Verilog HDL code, and completed the hardware. Paper describes the physical platform implementations and processes, analyzes the timing and resource consumption of each module, given the hardware implementation.