Implementation Of High-Dynamic BDS Anti-Jamming Algorithm Based On FPGA

In high-dynamic applications, such as aerospace, missile and high-speed aircraft guidance. The directions of arrival(DOA) of jamming changes rapidly and the nulls produced by conventional BDS anti-jamming receiver hardly direct at jamming when there exist jamming. It causes that the jamming can't be suppressed effectively, so the positioning accuracy of receiver is influenced seriously. Therefore, the development of high dynamic BDS anti-interference system has certain practical significance.To solve those problems, the design and implementation of high dynamic BDS anti-jamming system based on FPGA are discussed in this thesis. Firstly, the minimum power algorithm and covariance matrix taper(CMT) null-widen algorithm are analyzed. The high-dynamic real-time anti-jamming system is implemented with the method of speeding up the weight update rate and then realizing weights and data match in traditional minimum power algorithm. The proposed scheme is proven to be effective by comparing to other algorithms' suppression performance in the high-dynamic environment. Then, high dynamic anti-jamming system is implemented in hardware. Hardware and software design scheme, parameter configuration of high-dynamic BDS anti-jamming system are given. The process of system simulation and fix-point, parameter selection and modular design are elaborated. Finally, the validity of scheme is validated through hardware system test and high-dynamic simulation, the interference cancellation capability has been tested. Contraposing to actual testing requirements for system, remote control program of equipment is implemented based on Labview. More than one signal generators can be controlled remotely by computer and workload of testers is significantly reduced with this program. The high-dynamic BDS anti-jamming system implemented here possesses strong capability of suppressing interference and practical value.