Hardware Acceleration Engine Design For Financial IC Chip Based On State Cryptography

The traditional magnetism card is easy to clone, and there are a lot of frauds of fake cards. Therefore, the international EMV organization published a financial IC card standard and vigorously promoted the traditional magnetism card transfer to the financial IC card,called the “EMV migration”. Followed by the international EMV organization, the People's Bank of China proposed a financial IC card standard, PBOC3.0 in short, based on the state cryptography which is our own intellectual property right. For China's financial IC card industry, it's of great significance to research and design the financial IC chip that satisfy the PBOC3.0 standard.The cryptographic engine is the core security of financial IC chip. Thus, it's important to research and implement the state cryptography algorithm suitable for financial IC card application.PBOC3.0 standard include the complexity of the crypthgraphy needed is first studied and analysed. Then, the hardware system architecture for the financial IC chip is designed.An area efficient hardware cryptography accelerator engine satisfied PBOC3.0 standard is researched and realized. The SM2 is designed for offline data authentication and the SM4 is designed for security message protocol.Realization of SM2 algorithm. First, taking the high security needed for financial IC chip into consideration, a scalar multiplication resists against power analysis called double-add-always is adopted. Then, the coordinate transformation is used to reduce the complexity of Point Add and Point Double algorithm. A finite instruction state machine is designed to realize the PA&PD algorithm. The instruction scheduling is optimized to decrease the cycles needed. Besides, considering the limited resources of financial IC chip and tradeoff between area and speed, a large integer multiplication based on 64 bit multiply-accumulator is optimized. A fast modular reduction unit is designed for SM2. Onthe anther way, a unified modular addition and subtraction arithmetic unit is designed to reduce the number of logical circuits. Through the reasonable data path design, the PA&PD algorithm can be accomplished just using one modular multiplication and two unified modular addition and subtraction.Realization of SM4 algorithm. First, a circuit for constant CK parameter generation in real time is proposed. Then, the realization method of S-box is analyzed and optimized. In the end, through the analysis of SM4 algorithm, we can find than the data path for encryption and key expansion is almost the same. Thus, a sharing data path can be designed.Four different data path sharing structure with different sharing level is designed. The four structures are comparative studied, and their application situation is also discussed.After the design of the cryptography engine, the security functional simulation and FPGA emulation is done by this paper. It turns out that the design is totally correct. The ASIC implement of the design is done in SMIC 0.13?m EFlash technology. In the ASIC implement, the SM2 cryptography engine consumes 278788?m2 area, about 68.8k gate equipment. The max frequency can reach up to 127.8MHz. It takes 1347?s to accomplish the scalar multiplication, thus the throughput is 190 kbps. 16 cycles are needed for the256 bit modular multiplication. The throughput of modular multiplication is 2.046 Gbps.When comes to the SM4 algorithm. The designed 8bit serialized sharing data path can achieve a minimum area of 17987?m2, about 3824 gate equipment. The max frequency is120.7MHz and the throughput is 60.38 Mbps. It suits the financial IC application which needs low power and small area consumption. The designed financial IC chip is finally tape out in the MPW and total die size is 3200×2800?m2?All functional tests are passed, the actual power of the chip is 5~8mA on noamal mode and 900?A on sleep mode.