Design For Phase-locked Loop Of High-precision Duty Cycle And Low Jitter

SERDES is Serializer(SER, parallel a nd serial) and a deserializer(DES, serial converter) for short. SERDES its good transmission characteristics, widely used in communications systems. Phase-locked loop circuit as SERDES part of the system, the output clock signal on the one hand can be used to send and receive side, on the other hand can be used as a clock recovered clock signal. With the improvement of technology, domestic and foreign SERDES speed is increasing year by year, and SERDES clock signals provided by the PLL, so speed is a characteristic of the PLL. In addition to the high-speed characteristics, compared to other phase- locked loop circuit system, in order to meet the error rate requirements SERDES each module, the clock signal is low jitter PLL must be provided, so that the low j itter PLL is SERDES a major feature. O n the other hand, as part of the phase- locked loop clock recovery circuit, in order to meet the needs of the clock recovery circuit and a double-edge sampling phase, multi-phase delivery and provide high-precision duty cycle is SERDES two features in PLL. The main work is as follows.(1) In order to design a low-jitter PLL, starting with the basic principle of this article PLL starting to construct the mathematical phase- locked loop transfer function of each of the main modules, including closed- loop and open- loop, for lock ring design basis. On the other hand each module analyzes the noise phase-locked loop transfer function, the analysis of the specific parameters of each module in the noise transfer function in the relationship between the characteristics and the phase- locked loop bandwidth and to select the PLL.(2) Non- ideal effects of each module of the PLL from the departure of non- ideal effects for each module, each module proposed improvement measures. Which the PFD dead time, phase range is analyzed, designed a no dead zone, a wide range of phase PFD. CP's non-ideal effects are more, of which there are charge-sharing, clock feedthrough and so on, these non- ideal effects for this article, has designed a charge sharing and clock feedthrough effects are relatively small CP. VCO is a priority component this design, VCO structure directly related to the clock jitter, phase output, therefore design a low-jitter, four-phase VCO.(3) Since the clock recovery circuit, the clock signal duty cycle requirement is fifty percent. This article has been in the traditional duty cycle adjustment circuit for adjusting the duty cycle circuit may deviate from the fifty percent of cases, designed to adjust the duty cycle of a closed- loop circuit, by automatically adjusting well to the output a fifty percent duty cycle of the clock signal. While for the duty ratio adjusting circuit changes the frequency of the input clock signal, increasing the rapid response circuit in the circuit, improving the reaction speed of the circuit.(4) As a circuit layout design work completed, its design is directly related to the performance of the entire design and functionality. Aiming layout possible problems, proposed to avoid latch-effective, matching, protection ring design. And circuit simulation and layout verification of the functionality and performance of the entire design.