A Master-slave Delay Locked Loop With Low Jitter Applied To TDC

With the reduction of process feature size in Integrated circuit and the improvement of working speed,the performance of clock circuits applied for all kinds of circuit systems are more stringent.As a kind of time measurement circuit system,time-to-digital converter(TDC)has higher requirements on clock circuit in terms of jitter,the uniformity of different phase,duty cycle and the accuracy of delay time.Due to the characteristics of closed-loop negative feedback,delayed locked loop(DLL)has high process,power supply voltage and temperature(PVT)stability,and can be perfectly applied to TDC.In addition,DLL is widely used in other circuit systems,such as audio driver,memory and mobile communication.In this paper,a DLL circuit based on master-slave architecture is designed according to the requirement of TDC for clock circuit performance.The master DLL provides clock signal and Multi-phase clock for TDC,and the master and slave DLLs cooperate with each other to achieve ps-level resolution.Based on analysis of DLL loop theory,the key parameters of the DLL loop are determined.Optimizing the structure and parameters of each sub-module,strengthen the design of load matching on signal transmission path and improving the performance of duty cycle to satisfy the application requirements of TDC.Using bottom to up layout design method and channel routing technology to complete the overall layout design.In addition,the methods of separating digital and analog modules,shielding sensitive signal lines and isolating the modules with larger noise are used to improve the quality of clock signals.Based on TSMC 0.35?m CMOS process,the circuit and layout of master-slave DLL are completed on Cadence platform,and the simulation results of DLL meet the design specifications.The test results show that the function of master-slave DLL is normal,but its performance is degraded compared with the simulation results.The lock frequency range of DLL is 105MHz~210MHz,and at typical operating frequency of 125 MHz,the static phase error is-34 ps,the maximum phase error is +86 ps,the range of duty cycle error is-2.0%~+1.0%,the root mean square value and the peak to peak value of TIE jitter are 0.52 ps and 3.70 ps,the maximum delay difference is 29.8 ps,and the working current is 53 mA.The deterioration reasons of test results are analyzed in detail in this paper,and some feasible improvement schemes are given.