A Real-time Image Acquisition And Processing Display System Based On FPGA

Real-time image processing system on the image processing speed is relatively high,low-level image processing algorithm to repeat the same operation for many times because the software implementation of the serial processing speed is much slower than the parallel processing of hardware processing.FPGAs are ideal for hardware-based digital image processing because of parallel computing and repeatability.At present,FPGA-based image processing algorithm has become a hot research topic.In this thesis,an FPGA-based image acquisition and processing system is constructed.This system is mainly composed of image acquisition module,image chromaticity space conversion module,image processing module,image storage module and VGA control module.In this system,the edge filtering algorithm is realized based on the angle of smoothing noise,and the edge detection algorithm based on Sobel operator is realized by extracting the edge image.In order to optimize the marginal consistency of the edge image,the morphological filtering algorithm is realized Digital image processing algorithm.In this thesis,we focus on the design and implementation of the bilateral filter based on FPGA,and compare the performance of the bilateral filter and the common filter with the objective performance evaluation standard of the spatial filtering algorithm.And after implementing the edge filtering processing module and the morphological filter processing module,the objective performance and evaluation of the system processing module are proved by the objective performance evaluation standard of the edge filtering algorithm.In the design process of the whole system,the characteristics of the parallel operation of the digital image algorithm are taken into account,and the hardware of the image algorithm is used to accelerate the hardware.The system design simulation is realized by hardware description language programming on Quartus II platform,and it is verified on the hardware platform designed by Altera Corporation Cyclone IV series FPGA chip as the core design.In the final system test can be seen that the system can meet the processing requirements,in the FPGA platform to complete the acquisition and processing display system.This thesis attempts to achieve in the system is different from the FPGA platform on the common noise reduction filter edge better performance of the bilateral filter,and quantitative proof of the effectiveness and rationality of the system processing module.The noise reduction module effectively improves the error performance between pixels such as MAE,MSE and PSNR under the condition of almost no loss of SSIM and MSSIM.This thesis has a positive significance in smoothing noise in FPGA-based image processing system and optimizing the performance of edge image module.