Research On Clock Synchronization Mechanism Of Fault-Tolerant Time-Triggered Ethernet And Hardware Implementation

With the increasingly rich functionality of modern electronic systems,integrated modules become more and more complex,greater demands are being placed on bandwidth,delay,reliability and other indicators.Real-time Ethernet is the future direction of Ethernet development,and Time-triggered Ethernet(TTE)compared with other network technology has the traditional Ethernet compatibility advantage,which makes it become one of the most promising projects.Especially for industrial-grade Ethernet,national defense and aerospace field,the demand for strong real-time and high reliability makes this technology more and more development potential.This paper aims to find a strong real-time,high-bandwidth,high-reliability network transmission technology,to curry on relevant theoretical research and design algorithm and implementation,the research content is as follows:(1)Exploring and comparing among the TTP/C,FlexRay,ARINC659,TTE.Considering the better compatibility,good clock accuracy and fault-tolerant performance of TTE with traditional Ethernet,this study focuses on TTE as the main research object.(2)In this study,the AS6802 protocol is elaborately researched and the principle of dispatching and dispatching of different data frames in the network is deeply analyzed.The time curing algorithm and compression algorithm in TTE synchronization operation are mastered.The functions of the joint nodes SM,CM and SC in the network are deeply understood.The state of the state machine corresponding to the operation and state transition conditions;familiar with the TTE fault tolerance mechanism,understand the membership detection of fault tolerance method.(3)Based on the above research,the simulation design of TTE fault-tolerant clock synchronization mechanism is completed on OPNET.The model of the terminal node and the switch is established,and the SM,CM and SC state machine process models are designed to complete the verification of the TTE synchronization mechanism according to the different simulation scenarios.By setting the fault node parameters,the TTE fault tolerance mechanism is tested and verified.(4)The hardware module design of SM node is realized,and the function of the key module is simulated by Modelsim.According to the test results,TTE fault-tolerant clock synchronization mechanism is a complete set of clock synchronization and fault-tolerant solution;all aspects of performance have achieved the desired results with high precision synchronization and fault-tolerant performance.