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Reasrarch On High Precision Clock Synchronization Technology Of Time-triggered Ethernet

Posted on:2021-09-29Degree:MasterType:Thesis
Country:ChinaCandidate:K ZhangFull Text:PDF
GTID:2518306470467634Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
As the "nerve" and "skeleton" of aerospace integrated electronic system,the working efficiency of communication bus is directly related to the execution ability and system stability of aerospace business.With the rapid development of aerospace applications and the wide application of distributed systems,low transmission rate,low bandwidth,low fault tolerance and uncertain transmission delay become unprecedented technical challenges and thorny problems for communication bus.Due to the strict communication requirements of real-time,certainty and security in the aerospace field,the traditional bus is often not competent,so time triggered Ethernet emerges as the times require.As a new communication bus of the new generation Aerospace integrated electronic system,Time-Triggered Ethernet(TTEthernet)adds time triggered mechanism on the basis of standard Ethernet,and adopts high-precision clock synchronization technology to ensure the real-time communication and time certainty in the data transmission process of aerospace integrated electronic system.Therefore,high-precision clock synchronization mechanism has become a research hotspot of time triggered Ethernet technology.Based on time triggered Ethernet,this paper focuses on the research of highprecision clock synchronization:(1)The development status,architecture,communication mechanism and fault tolerance scheme of Time Triggered Ethernet technology are systematically described.In this paper,the Time-Triggered Ethernet SAE AS6802 clock synchronization protocol is studied,and the main algorithm of the protocol is realized on the basis of fully understanding its synchronization process.(2)According to Time-Trigger Ethernet SAE AS6802 clock synchronization protocol,a hierarchical network simulation modeling methods of time trigger Ethernet scenario,node model and process model for overall modeling,on this basis,set up the simulation platform to realize the network time synchronization algorithm,using network calculus to further verify the clock synchronization precision and network performance.The results show that under the premise of clock phase and frequency errors in the network,SAE AS6802 clock synchronization protocol can effectively eliminate the phase errors and suppress part of the frequency errors,and the overall clock synchronization accuracy can reach 100 ns level.(3)Aiming at the clock frequency offset caused by the failure of Time-Triggered Ethernet SAE AS6802 to compensate crystal frequency,a high-precision clock synchronization optimization scheme based on crystal frequency digital compensation technology is proposed.The node local clock model of time triggered Ethernet is established,and the corresponding clock frequency compensation module is designed.By embedding the look-up table into the crystal frequency digital compensation circuit,the crystal frequency is compensated periodically according to the "temperature ppm" characteristic curve of crystal oscillator.The hardware simulation platform is built,the optimized time triggered Ethernet node is modeled,the function is simulated by Modelsim software,and the hardware overhead of network node is analyzed by DC software.The research results show that under the same error parameters,the clock synchronization accuracy is improved to 10 ns level based on the scheme of crystal frequency digital compensation,which greatly improves the time synchronization accuracy of time triggered Ethernet.
Keywords/Search Tags:Time Triggered Ethernet, clock synchronization, network calculus and simulation, network modeling, crystal frequency oscillator digital compensation
PDF Full Text Request
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