Research Of CMOS Oscillator For High Performance PLL Application

The flourishing of ubiquitous wireless communication networks has significantly promoted the development of complex RF systems.Fully-integrated RF circuits,including oscillators,have been playing a key role in such systems.The performances of the oscillator,such as operating frequency,operating range,phase noise,power consumption,are the key bottlenecks of the system.Certainly,the requirements vary considerably in different applications.At millimeter-wave range,for example,a low power operation is highly desired when the requirements of working range and phase noise can be satisfied.At GHz range,however,where power consumption is much lower,a wide operating range and small silicon area are major considerations.The popular solutions of oscillator have been reviewed and analyzed.Based on these considerations,several oscillators have been designed and verified.The key considerations of low power injection-locked oscillator(ILO)are analyzed.Using a supply injection topology,the proposed ILO is able to work at lower supply voltage with a good balance of other performances.Fabricated in Tower JAZZ 0.18μm SiGe BiCMOS technology,a prototype of ILO with supply injection achieves an operating frequency of 53.2GHz.Occupying a silicon area of 0.24mm~2,the core circuit consumes 3mW from a 0.7V power supply.Secondly,the wide-range voltage-controlled oscillator(VCO)at GHz where constant Kvco and low phase noise are key considerations,is analyzed and designed.A 5-bits 3.62 to 4.35GHz CMOS VCO is presented in this work.The tuning gain varies from 73.8MHz/(0.8V)to 75.9MHz/(0.8V).The variations of Kvco have been reduced considerably while a good phase noise of-117dBc/Hz@1MHz has been reached.Finally,several new techniques such as active inductors and active transformers have been used in current mode phase locked loop(PLL).Instead of using traditional passive loop filter,the silicon area of the proposed current controlled oscillator(CCO)has been reduced significantly.A 5.12 to 5.4GHz current controlled phase locked loop(CCPLL)occupying only 8100μm2 chip area of core circuit is designed and simulated using a 130nm CMOS technology.