New Additive-Calibration Scheme For Leakage Compensation Of Low Voltage SRAM

As the progress of the semiconductor process,SRAM is moving in the direction of high speed and low power consumption.Unfortunately,the bit-line leakage current is becoming bigger and bigger.The performance of SRAM would deteriorate as the bit-line leakage increases.Especially,the read operation will even fail when the amount of the leakage reaches a critical value.Therefore,it is very important to study the leakage.The paper is organized as follows:1.First,it introduces three kinds of basic operations of the SRAM,i.e.read operation,write operation and standby operation.And then we introduce some existing classical leakage-solving techniques,i.e.the BLC scheme,the X-calibration scheme and the bit-line positive feedback compensation scheme.We analyze their principle in detail and summarize their advantages and disadvantages.2.In order to boost the drive capability of the sense amplifier and reduce it’s read time,we propose an improvement project based on the X-calibration circuit,called the Additive Calibration scheme(AC).The simulation results show that the AC scheme takes less time to read out the data and improves performance of the SRAM.However,the maximum tolerant bit-line leakage current of the AC scheme is similar as the XC.And AC also needs a longer leakage detection time.So,it can not work well at a high frequency.Fortunately,the AC scheme can also be improved to solve these disadvantages.3.We improve the circuit from 2 and add an operation called the 2nd pre-charge.Then we get the New Additive Calibration(NAC)circuit.The main feature of the NAC is the adjustment of the timing.The advantages of our NAC are not only boosting the drive capability of the sense amplifier as the AC scheme,what’s more,the NAC can stand bigger leakage current than AC.It follows the tendency of the leakage compensation technology.The simulation results show that the NAC scheme can stand 119%and 45.5%higher bit-line leakage current than the conventional and the XC scheme,respectively,based on the 65-nm SMIC CMOS technology.Thus,this method can perform at higher frequency with much lower power consumption.